/*
 * ARM Limited (ARM) is supplying this software for use with Cortex-M
 * processor based microcontroller, but can be equally used for other
 * suitable processor architectures. This file can be freely distributed.
 * Modifications to this file shall be clearly marked.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 * @file     a34m41x.h
 * @brief    CMSIS HeaderFile
 * @version  1.0
 * @date     13. November 2020
 * @note     Generated by SVDConv V3.2.66 on Friday, 13.11.2020 16:39:18
 *           from File 'a34m41x.svd',
 *           last modified on Friday, 13.11.2020 07:39:01
 */



/** @addtogroup ABOV Semiconductor Co., Ltd.
  * @{
  */


/** @addtogroup a34m41x
  * @{
  */


#ifndef A34M41X_H
#define A34M41X_H

#ifdef __cplusplus
extern "C" {
#endif


/** @addtogroup Configuration_of_CMSIS
  * @{
  */



/* =========================================================================================================================== */
/* ================                                Interrupt Number Definition                                ================ */
/* =========================================================================================================================== */

/* ================                           Processor and Core Peripheral Section                           ================ */
/* =========================================================================================================================== */

/* ===========================  Configuration of the ARM Cortex-M4 Processor and Core Peripherals  =========================== */
#define __CM4_REV                 0x0001U       /*!< CM4 Core Revision                                                         */
#define __NVIC_PRIO_BITS               4        /*!< Number of Bits used for Priority Levels                                   */
#define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
#define __MPU_PRESENT                  1        /*!< MPU present or not                                                        */
#define __FPU_PRESENT                  1        /*!< FPU present or not                                                        */


/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm4.h"                           /*!< ARM Cortex-M4 processor and core peripherals                              */
//#include "a34m41x_system.h"                     /*!< a34m41x System                                                            */

#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __IM   __I
#endif
#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __OM   __O
#endif
#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
  #define __IOM  __IO
#endif


/* ========================================  Start of section using anonymous unions  ======================================== */
#if defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
  #pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif


/* =========================================================================================================================== */
/* ================                            Device Specific Peripheral Section                             ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                            PA                                             ================ */
/* =========================================================================================================================== */


/**
  * @brief General Port (PA)
  */

typedef struct {                                /*!< (@ 0x40001000) PA Structure                                               */
  __IOM uint32_t  MR1;                          /*!< (@ 0x00000000) Port n MUX1 Selection Register                             */
  __IOM uint32_t  MR2;                          /*!< (@ 0x00000004) Port n MUX2 Selection Register                             */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000008) Port n Type Selection Register                             */
  __IOM uint32_t  PRCR;                         /*!< (@ 0x0000000C) Port n Pull-up/down Selection Register                     */
  __IOM uint32_t  DER;                          /*!< (@ 0x00000010) Port n Debounce Enable Register                            */
  __IOM uint32_t  STR;                          /*!< (@ 0x00000014) Port n Strength Selection Register                         */
  __IM  uint32_t  RESERVED[2];
  __IOM uint32_t  IER;                          /*!< (@ 0x00000020) Port n Interrupt Enable Register                           */
  __IOM uint32_t  ISR;                          /*!< (@ 0x00000024) Port n Interrupt Status Register                           */
  __IOM uint32_t  ICR;                          /*!< (@ 0x00000028) Port n Interrupt Control Register                          */
  __IM  uint32_t  RESERVED1;
  __IOM uint32_t  ODR;                          /*!< (@ 0x00000030) Port n Output Data Register                                */
  __IM  uint32_t  IDR;                          /*!< (@ 0x00000034) Port n Input Data Register                                 */
  __OM  uint32_t  PSR;                          /*!< (@ 0x00000038) Port n Bit Set Register                                    */
  __OM  uint32_t  PCR;                          /*!< (@ 0x0000003C) Port n Bit Clear Register                                  */
} PCU_Type;                                     /*!< Size = 64 (0x40)                                                          */



/* =========================================================================================================================== */
/* ================                                          PORTEN                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief General Port Access Enable (PORTEN)
  */

typedef struct {                                /*!< (@ 0x40001FF0) PORTEN Structure                                           */
  __OM  uint32_t  EN;                           /*!< (@ 0x00000000) Port Access Enable Register                                */
} PORTEN_Type;                                  /*!< Size = 4 (0x4)                                                            */



/** @} */ /* End of group Device_Peripheral_peripherals */


/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripheralAddr
  * @{
  */

#define CHIPCONFIG_BASE             0x4000F000UL
#define SCU_BASE                    0x40000000UL
#define PA_BASE                     0x40001000UL
#define PB_BASE                     0x40001100UL
#define PC_BASE                     0x40001200UL
#define PD_BASE                     0x40001300UL
#define PE_BASE                     0x40001400UL
#define PF_BASE                     0x40001500UL
#define PG_BASE                     0x40001600UL
#define PORTEN_BASE                 0x40001FF0UL
#define CFMC_BASE                   0x41000000UL
#define DFMC_BASE                   0x41001000UL
#define DMA0_BASE                   0x40000400UL
#define DMA1_BASE                   0x40000410UL
#define DMA2_BASE                   0x40000420UL
#define DMA3_BASE                   0x40000430UL
#define DMA4_BASE                   0x40000440UL
#define DMA5_BASE                   0x40000450UL
#define DMA6_BASE                   0x40000460UL
#define DMA7_BASE                   0x40000470UL
#define DMA8_BASE                   0x40000480UL
#define DMA9_BASE                   0x40000490UL
#define DMA10_BASE                  0x400004A0UL
#define DMA11_BASE                  0x400004B0UL
#define DMA12_BASE                  0x400004C0UL
#define DMA13_BASE                  0x400004D0UL
#define DMA14_BASE                  0x400004E0UL
#define DMA15_BASE                  0x400004F0UL
#define WDT_BASE                    0x40000200UL
#define TIMER0_BASE                 0x40003000UL
#define TIMER1_BASE                 0x40003040UL
#define TIMER2_BASE                 0x40003080UL
#define TIMER3_BASE                 0x400030C0UL
#define TIMER4_BASE                 0x40003100UL
#define TIMER5_BASE                 0x40003140UL
#define TIMER6_BASE                 0x40003180UL
#define TIMER7_BASE                 0x400031C0UL
#define TIMER8_BASE                 0x40003200UL
#define TIMER9_BASE                 0x40003240UL
#define FRT0_BASE                   0x40000600UL
#define FRT1_BASE                   0x40000700UL
#define UART0_BASE                  0x40008000UL
#define UART1_BASE                  0x40008100UL
#define UART2_BASE                  0x40008200UL
#define UART3_BASE                  0x40008300UL
#define UART4_BASE                  0x40008400UL
#define UART5_BASE                  0x40008500UL
#define SPI0_BASE                   0x40009000UL
#define SPI1_BASE                   0x40009100UL
#define SPI2_BASE                   0x40009200UL
#define I2C0_BASE                   0x4000A000UL
#define I2C1_BASE                   0x4000A100UL
#define CAN_BASE                    0x40007000UL
#define MPWM0_BASE                  0x40004000UL
#define MPWM1_BASE                  0x40005000UL
#define QEI0_BASE                   0x4000B400UL
#define QEI1_BASE                   0x4000B500UL
#define ADC0_BASE                   0x4000B000UL
#define ADC1_BASE                   0x4000B100UL
#define ADC2_BASE                   0x4000B200UL
#define PGA0_BASE                   0x4000B300UL
#define PGA1_BASE                   0x4000B304UL
#define PGA2_BASE                   0x4000B308UL
#define COMP0_BASE                  0x4000B380UL
#define COMP1_BASE                  0x4000B38CUL
#define COMP2_BASE                  0x4000B398UL
#define COMP3_BASE                  0x4000B3A4UL
#define AES128_BASE                 0x40000500UL
#define RNG_BASE                    0x40000A00UL
#define CRC_BASE                    0x41002000UL

/** @} */ /* End of group Device_Peripheral_peripheralAddr */


/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_declaration
  * @{
  */

#define CHIPCONFIG                  ((CHIPCONFIG_Type*)        CHIPCONFIG_BASE)
#define SCU                         ((SCU_Type*)               SCU_BASE)
#define PA                          ((PCU_Type*)               PA_BASE)
#define PB                          ((PCU_Type*)               PB_BASE)
#define PC                          ((PCU_Type*)               PC_BASE)
#define PD                          ((PCU_Type*)               PD_BASE)
#define PE                          ((PCU_Type*)               PE_BASE)
#define PF                          ((PCU_Type*)               PF_BASE)
#define PG                          ((PCU_Type*)               PG_BASE)
//#define PORTEN                      ((PORTEN_Type*)            PORTEN_BASE)
#define CFMC                        ((CFMC_Type*)              CFMC_BASE)
#define DFMC                        ((DFMC_Type*)              DFMC_BASE)
#define DMA0                        ((DMA_Type*)               DMA0_BASE)
#define DMA1                        ((DMA_Type*)               DMA1_BASE)
#define DMA2                        ((DMA_Type*)               DMA2_BASE)
#define DMA3                        ((DMA_Type*)               DMA3_BASE)
#define DMA4                        ((DMA_Type*)               DMA4_BASE)
#define DMA5                        ((DMA_Type*)               DMA5_BASE)
#define DMA6                        ((DMA_Type*)               DMA6_BASE)
#define DMA7                        ((DMA_Type*)               DMA7_BASE)
#define DMA8                        ((DMA_Type*)               DMA8_BASE)
#define DMA9                        ((DMA_Type*)               DMA9_BASE)
#define DMA10                       ((DMA_Type*)               DMA10_BASE)
#define DMA11                       ((DMA_Type*)               DMA11_BASE)
#define DMA12                       ((DMA_Type*)               DMA12_BASE)
#define DMA13                       ((DMA_Type*)               DMA13_BASE)
#define DMA14                       ((DMA_Type*)               DMA14_BASE)
#define DMA15                       ((DMA_Type*)               DMA15_BASE)
#define WDT                         ((WDT_Type*)               WDT_BASE)
/*
*/
#define FRT0                        ((FRT_Type*)               FRT0_BASE)
#define FRT1                        ((FRT_Type*)               FRT1_BASE)
//#define UART0                       ((UART_Type*)              UART0_BASE)
//#define UART1                       ((UART_Type*)              UART1_BASE)
//#define UART2                       ((UART_Type*)              UART2_BASE)
//#define UART3                       ((UART_Type*)              UART3_BASE)
//#define UART4                       ((UART_Type*)              UART4_BASE)
//#define UART5                       ((UART_Type*)              UART5_BASE)
//#define SPI0                        ((SPI_Type*)               SPI0_BASE)
//#define SPI1                        ((SPI_Type*)               SPI1_BASE)
//#define SPI2                        ((SPI_Type*)               SPI2_BASE)
//#define I2C0                        ((I2C_Type*)               I2C0_BASE)
//#define I2C1                        ((I2C_Type*)               I2C1_BASE)
#define CAN                         ((CAN_Type*)               CAN_BASE)
//#define MPWM0                       ((MPWM_Type*)              MPWM0_BASE)
//#define MPWM1                       ((MPWM_Type*)              MPWM1_BASE)
#define QEI0                        ((QEI_Type*)               QEI0_BASE)
#define QEI1                        ((QEI_Type*)               QEI1_BASE)
//#define ADC0                        ((ADC_Type*)               ADC0_BASE)
//#define ADC1                        ((ADC_Type*)               ADC1_BASE)
//#define ADC2                        ((ADC_Type*)               ADC2_BASE)
#define PGA0                        ((PGA_Type*)               PGA0_BASE)
#define PGA1                        ((PGA_Type*)               PGA1_BASE)
#define PGA2                        ((PGA_Type*)               PGA2_BASE)
#define COMP0                       ((COMP_Type*)              COMP0_BASE)
#define COMP1                       ((COMP_Type*)              COMP1_BASE)
#define COMP2                       ((COMP_Type*)              COMP2_BASE)
#define COMP3                       ((COMP_Type*)              COMP3_BASE)
#define AES128                      ((AES128_Type*)            AES128_BASE)
#define RNG                         ((RNG_Type*)               RNG_BASE)
#define CRC                         ((CRC_Type*)               CRC_BASE)

/** @} */ /* End of group Device_Peripheral_declaration */


/* =========================================  End of section using anonymous unions  ========================================= */
#if defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#endif


/* =========================================================================================================================== */
/* ================                                Pos/Mask Peripheral Section                                ================ */
/* =========================================================================================================================== */


/** @addtogroup PosMask_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                        CHIPCONFIG                                         ================ */
/* =========================================================================================================================== */

/* =======================================================  VENDORID  ======================================================== */
/* ========================================================  CHIPID  ========================================================= */
/* =========================================================  REVNR  ========================================================= */


/* =========================================================================================================================== */
/* ================                                            SCU                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  SMR  ========================================================== */
#define SCU_SMR_LSEAON_Pos                (13UL)                    /*!< SCU SMR: LSEAON (Bit 13)                              */
#define SCU_SMR_LSEAON_Msk                (0x2000UL)                /*!< SCU SMR: LSEAON (Bitfield-Mask: 0x01)                 */
#define SCU_SMR_HSEAON_Pos                (12UL)                    /*!< SCU SMR: HSEAON (Bit 12)                              */
#define SCU_SMR_HSEAON_Msk                (0x1000UL)                /*!< SCU SMR: HSEAON (Bitfield-Mask: 0x01)                 */
#define SCU_SMR_PLLAON_Pos                (11UL)                    /*!< SCU SMR: PLLAON (Bit 11)                              */
#define SCU_SMR_PLLAON_Msk                (0x800UL)                 /*!< SCU SMR: PLLAON (Bitfield-Mask: 0x01)                 */
#define SCU_SMR_HSIAON_Pos                (10UL)                    /*!< SCU SMR: HSIAON (Bit 10)                              */
#define SCU_SMR_HSIAON_Msk                (0x400UL)                 /*!< SCU SMR: HSIAON (Bitfield-Mask: 0x01)                 */
#define SCU_SMR_LSIAON_Pos                (9UL)                     /*!< SCU SMR: LSIAON (Bit 9)                               */
#define SCU_SMR_LSIAON_Msk                (0x200UL)                 /*!< SCU SMR: LSIAON (Bitfield-Mask: 0x01)                 */
#define SCU_SMR_VDCAON_Pos                (8UL)                     /*!< SCU SMR: VDCAON (Bit 8)                               */
#define SCU_SMR_VDCAON_Msk                (0x100UL)                 /*!< SCU SMR: VDCAON (Bitfield-Mask: 0x01)                 */
#define SCU_SMR_PREVMODE_Pos              (4UL)                     /*!< SCU SMR: PREVMODE (Bit 4)                             */
#define SCU_SMR_PREVMODE_Msk              (0x30UL)                  /*!< SCU SMR: PREVMODE (Bitfield-Mask: 0x03)               */
/* =========================================================  SRCR  ========================================================== */
#define SCU_SRCR_STBYO_Pos                (4UL)                     /*!< SCU SRCR: STBYO (Bit 4)                               */
#define SCU_SRCR_STBYO_Msk                (0x10UL)                  /*!< SCU SRCR: STBYO (Bitfield-Mask: 0x01)                 */
#define SCU_SRCR_SWRST_Pos                (0UL)                     /*!< SCU SRCR: SWRST (Bit 0)                               */
#define SCU_SRCR_SWRST_Msk                (0x1UL)                   /*!< SCU SRCR: SWRST (Bitfield-Mask: 0x01)                 */
/* =========================================================  WUER  ========================================================== */
#define SCU_WUER_GPIOGWUE_Pos             (14UL)                    /*!< SCU WUER: GPIOGWUE (Bit 14)                           */
#define SCU_WUER_GPIOGWUE_Msk             (0x4000UL)                /*!< SCU WUER: GPIOGWUE (Bitfield-Mask: 0x01)              */
#define SCU_WUER_GPIOFWUE_Pos             (13UL)                    /*!< SCU WUER: GPIOFWUE (Bit 13)                           */
#define SCU_WUER_GPIOFWUE_Msk             (0x2000UL)                /*!< SCU WUER: GPIOFWUE (Bitfield-Mask: 0x01)              */
#define SCU_WUER_GPIOEWUE_Pos             (12UL)                    /*!< SCU WUER: GPIOEWUE (Bit 12)                           */
#define SCU_WUER_GPIOEWUE_Msk             (0x1000UL)                /*!< SCU WUER: GPIOEWUE (Bitfield-Mask: 0x01)              */
#define SCU_WUER_GPIODWUE_Pos             (11UL)                    /*!< SCU WUER: GPIODWUE (Bit 11)                           */
#define SCU_WUER_GPIODWUE_Msk             (0x800UL)                 /*!< SCU WUER: GPIODWUE (Bitfield-Mask: 0x01)              */
#define SCU_WUER_GPIOCWUE_Pos             (10UL)                    /*!< SCU WUER: GPIOCWUE (Bit 10)                           */
#define SCU_WUER_GPIOCWUE_Msk             (0x400UL)                 /*!< SCU WUER: GPIOCWUE (Bitfield-Mask: 0x01)              */
#define SCU_WUER_GPIOBWUE_Pos             (9UL)                     /*!< SCU WUER: GPIOBWUE (Bit 9)                            */
#define SCU_WUER_GPIOBWUE_Msk             (0x200UL)                 /*!< SCU WUER: GPIOBWUE (Bitfield-Mask: 0x01)              */
#define SCU_WUER_GPIOAWUE_Pos             (8UL)                     /*!< SCU WUER: GPIOAWUE (Bit 8)                            */
#define SCU_WUER_GPIOAWUE_Msk             (0x100UL)                 /*!< SCU WUER: GPIOAWUE (Bitfield-Mask: 0x01)              */
#define SCU_WUER_FRT1WUE_Pos              (3UL)                     /*!< SCU WUER: FRT1WUE (Bit 3)                             */
#define SCU_WUER_FRT1WUE_Msk              (0x8UL)                   /*!< SCU WUER: FRT1WUE (Bitfield-Mask: 0x01)               */
#define SCU_WUER_FRT0WUE_Pos              (2UL)                     /*!< SCU WUER: FRT0WUE (Bit 2)                             */
#define SCU_WUER_FRT0WUE_Msk              (0x4UL)                   /*!< SCU WUER: FRT0WUE (Bitfield-Mask: 0x01)               */
#define SCU_WUER_WDTWUE_Pos               (1UL)                     /*!< SCU WUER: WDTWUE (Bit 1)                              */
#define SCU_WUER_WDTWUE_Msk               (0x2UL)                   /*!< SCU WUER: WDTWUE (Bitfield-Mask: 0x01)                */
#define SCU_WUER_LVDWUE_Pos               (0UL)                     /*!< SCU WUER: LVDWUE (Bit 0)                              */
#define SCU_WUER_LVDWUE_Msk               (0x1UL)                   /*!< SCU WUER: LVDWUE (Bitfield-Mask: 0x01)                */
/* =========================================================  WUSR  ========================================================== */
#define SCU_WUSR_GPIOGWU_Pos              (14UL)                    /*!< SCU WUSR: GPIOGWU (Bit 14)                            */
#define SCU_WUSR_GPIOGWU_Msk              (0x4000UL)                /*!< SCU WUSR: GPIOGWU (Bitfield-Mask: 0x01)               */
#define SCU_WUSR_GPIOFWU_Pos              (13UL)                    /*!< SCU WUSR: GPIOFWU (Bit 13)                            */
#define SCU_WUSR_GPIOFWU_Msk              (0x2000UL)                /*!< SCU WUSR: GPIOFWU (Bitfield-Mask: 0x01)               */
#define SCU_WUSR_GPIOEWU_Pos              (12UL)                    /*!< SCU WUSR: GPIOEWU (Bit 12)                            */
#define SCU_WUSR_GPIOEWU_Msk              (0x1000UL)                /*!< SCU WUSR: GPIOEWU (Bitfield-Mask: 0x01)               */
#define SCU_WUSR_GPIODWU_Pos              (11UL)                    /*!< SCU WUSR: GPIODWU (Bit 11)                            */
#define SCU_WUSR_GPIODWU_Msk              (0x800UL)                 /*!< SCU WUSR: GPIODWU (Bitfield-Mask: 0x01)               */
#define SCU_WUSR_GPIOCWU_Pos              (10UL)                    /*!< SCU WUSR: GPIOCWU (Bit 10)                            */
#define SCU_WUSR_GPIOCWU_Msk              (0x400UL)                 /*!< SCU WUSR: GPIOCWU (Bitfield-Mask: 0x01)               */
#define SCU_WUSR_GPIOBWU_Pos              (9UL)                     /*!< SCU WUSR: GPIOBWU (Bit 9)                             */
#define SCU_WUSR_GPIOBWU_Msk              (0x200UL)                 /*!< SCU WUSR: GPIOBWU (Bitfield-Mask: 0x01)               */
#define SCU_WUSR_GPIOAWU_Pos              (8UL)                     /*!< SCU WUSR: GPIOAWU (Bit 8)                             */
#define SCU_WUSR_GPIOAWU_Msk              (0x100UL)                 /*!< SCU WUSR: GPIOAWU (Bitfield-Mask: 0x01)               */
#define SCU_WUSR_FRT1WU_Pos               (3UL)                     /*!< SCU WUSR: FRT1WU (Bit 3)                              */
#define SCU_WUSR_FRT1WU_Msk               (0x8UL)                   /*!< SCU WUSR: FRT1WU (Bitfield-Mask: 0x01)                */
#define SCU_WUSR_FRT0WU_Pos               (2UL)                     /*!< SCU WUSR: FRT0WU (Bit 2)                              */
#define SCU_WUSR_FRT0WU_Msk               (0x4UL)                   /*!< SCU WUSR: FRT0WU (Bitfield-Mask: 0x01)                */
#define SCU_WUSR_WDTWU_Pos                (1UL)                     /*!< SCU WUSR: WDTWU (Bit 1)                               */
#define SCU_WUSR_WDTWU_Msk                (0x2UL)                   /*!< SCU WUSR: WDTWU (Bitfield-Mask: 0x01)                 */
#define SCU_WUSR_LVDWU_Pos                (0UL)                     /*!< SCU WUSR: LVDWU (Bit 0)                               */
#define SCU_WUSR_LVDWU_Msk                (0x1UL)                   /*!< SCU WUSR: LVDWU (Bitfield-Mask: 0x01)                 */
/* =========================================================  RSER  ========================================================== */
#define SCU_RSER_LOCKUPRST_Pos            (9UL)                     /*!< SCU RSER: LOCKUPRST (Bit 9)                           */
#define SCU_RSER_LOCKUPRST_Msk            (0x200UL)                 /*!< SCU RSER: LOCKUPRST (Bitfield-Mask: 0x01)             */
#define SCU_RSER_PINRST_Pos               (7UL)                     /*!< SCU RSER: PINRST (Bit 7)                              */
#define SCU_RSER_PINRST_Msk               (0x80UL)                  /*!< SCU RSER: PINRST (Bitfield-Mask: 0x01)                */
#define SCU_RSER_CPURST_Pos               (6UL)                     /*!< SCU RSER: CPURST (Bit 6)                              */
#define SCU_RSER_CPURST_Msk               (0x40UL)                  /*!< SCU RSER: CPURST (Bitfield-Mask: 0x01)                */
#define SCU_RSER_SWRST_Pos                (5UL)                     /*!< SCU RSER: SWRST (Bit 5)                               */
#define SCU_RSER_SWRST_Msk                (0x20UL)                  /*!< SCU RSER: SWRST (Bitfield-Mask: 0x01)                 */
#define SCU_RSER_WDTRST_Pos               (4UL)                     /*!< SCU RSER: WDTRST (Bit 4)                              */
#define SCU_RSER_WDTRST_Msk               (0x10UL)                  /*!< SCU RSER: WDTRST (Bitfield-Mask: 0x01)                */
#define SCU_RSER_MCKFRST_Pos              (3UL)                     /*!< SCU RSER: MCKFRST (Bit 3)                             */
#define SCU_RSER_MCKFRST_Msk              (0x8UL)                   /*!< SCU RSER: MCKFRST (Bitfield-Mask: 0x01)               */
#define SCU_RSER_LSEFRST_Pos              (2UL)                     /*!< SCU RSER: LSEFRST (Bit 2)                             */
#define SCU_RSER_LSEFRST_Msk              (0x4UL)                   /*!< SCU RSER: LSEFRST (Bitfield-Mask: 0x01)               */
#define SCU_RSER_HSEFRST_Pos              (1UL)                     /*!< SCU RSER: HSEFRST (Bit 1)                             */
#define SCU_RSER_HSEFRST_Msk              (0x2UL)                   /*!< SCU RSER: HSEFRST (Bitfield-Mask: 0x01)               */
#define SCU_RSER_LVDRST_Pos               (0UL)                     /*!< SCU RSER: LVDRST (Bit 0)                              */
#define SCU_RSER_LVDRST_Msk               (0x1UL)                   /*!< SCU RSER: LVDRST (Bitfield-Mask: 0x01)                */
/* =========================================================  RSSR  ========================================================== */
#define SCU_RSSR_LOCKUPRST_Pos            (9UL)                     /*!< SCU RSSR: LOCKUPRST (Bit 9)                           */
#define SCU_RSSR_LOCKUPRST_Msk            (0x200UL)                 /*!< SCU RSSR: LOCKUPRST (Bitfield-Mask: 0x01)             */
#define SCU_RSSR_PORST_Pos                (8UL)                     /*!< SCU RSSR: PORST (Bit 8)                               */
#define SCU_RSSR_PORST_Msk                (0x100UL)                 /*!< SCU RSSR: PORST (Bitfield-Mask: 0x01)                 */
#define SCU_RSSR_PINRST_Pos               (7UL)                     /*!< SCU RSSR: PINRST (Bit 7)                              */
#define SCU_RSSR_PINRST_Msk               (0x80UL)                  /*!< SCU RSSR: PINRST (Bitfield-Mask: 0x01)                */
#define SCU_RSSR_CPURST_Pos               (6UL)                     /*!< SCU RSSR: CPURST (Bit 6)                              */
#define SCU_RSSR_CPURST_Msk               (0x40UL)                  /*!< SCU RSSR: CPURST (Bitfield-Mask: 0x01)                */
#define SCU_RSSR_SWRST_Pos                (5UL)                     /*!< SCU RSSR: SWRST (Bit 5)                               */
#define SCU_RSSR_SWRST_Msk                (0x20UL)                  /*!< SCU RSSR: SWRST (Bitfield-Mask: 0x01)                 */
#define SCU_RSSR_WDTRST_Pos               (4UL)                     /*!< SCU RSSR: WDTRST (Bit 4)                              */
#define SCU_RSSR_WDTRST_Msk               (0x10UL)                  /*!< SCU RSSR: WDTRST (Bitfield-Mask: 0x01)                */
#define SCU_RSSR_MCKFRST_Pos              (3UL)                     /*!< SCU RSSR: MCKFRST (Bit 3)                             */
#define SCU_RSSR_MCKFRST_Msk              (0x8UL)                   /*!< SCU RSSR: MCKFRST (Bitfield-Mask: 0x01)               */
#define SCU_RSSR_LSEFRST_Pos              (2UL)                     /*!< SCU RSSR: LSEFRST (Bit 2)                             */
#define SCU_RSSR_LSEFRST_Msk              (0x4UL)                   /*!< SCU RSSR: LSEFRST (Bitfield-Mask: 0x01)               */
#define SCU_RSSR_HSEFRST_Pos              (1UL)                     /*!< SCU RSSR: HSEFRST (Bit 1)                             */
#define SCU_RSSR_HSEFRST_Msk              (0x2UL)                   /*!< SCU RSSR: HSEFRST (Bitfield-Mask: 0x01)               */
#define SCU_RSSR_LVDRST_Pos               (0UL)                     /*!< SCU RSSR: LVDRST (Bit 0)                              */
#define SCU_RSSR_LVDRST_Msk               (0x1UL)                   /*!< SCU RSSR: LVDRST (Bitfield-Mask: 0x01)                */
/* =========================================================  PRER1  ========================================================= */
#define SCU_PRER1_QEI1_Pos                (29UL)                    /*!< SCU PRER1: QEI1 (Bit 29)                              */
#define SCU_PRER1_QEI1_Msk                (0x20000000UL)            /*!< SCU PRER1: QEI1 (Bitfield-Mask: 0x01)                 */
#define SCU_PRER1_QEI0_Pos                (28UL)                    /*!< SCU PRER1: QEI0 (Bit 28)                              */
#define SCU_PRER1_QEI0_Msk                (0x10000000UL)            /*!< SCU PRER1: QEI0 (Bitfield-Mask: 0x01)                 */
#define SCU_PRER1_TIMER9_Pos              (25UL)                    /*!< SCU PRER1: TIMER9 (Bit 25)                            */
#define SCU_PRER1_TIMER9_Msk              (0x2000000UL)             /*!< SCU PRER1: TIMER9 (Bitfield-Mask: 0x01)               */
#define SCU_PRER1_TIMER8_Pos              (24UL)                    /*!< SCU PRER1: TIMER8 (Bit 24)                            */
#define SCU_PRER1_TIMER8_Msk              (0x1000000UL)             /*!< SCU PRER1: TIMER8 (Bitfield-Mask: 0x01)               */
#define SCU_PRER1_TIMER7_Pos              (23UL)                    /*!< SCU PRER1: TIMER7 (Bit 23)                            */
#define SCU_PRER1_TIMER7_Msk              (0x800000UL)              /*!< SCU PRER1: TIMER7 (Bitfield-Mask: 0x01)               */
#define SCU_PRER1_TIMER6_Pos              (22UL)                    /*!< SCU PRER1: TIMER6 (Bit 22)                            */
#define SCU_PRER1_TIMER6_Msk              (0x400000UL)              /*!< SCU PRER1: TIMER6 (Bitfield-Mask: 0x01)               */
#define SCU_PRER1_TIMER5_Pos              (21UL)                    /*!< SCU PRER1: TIMER5 (Bit 21)                            */
#define SCU_PRER1_TIMER5_Msk              (0x200000UL)              /*!< SCU PRER1: TIMER5 (Bitfield-Mask: 0x01)               */
#define SCU_PRER1_TIMER4_Pos              (20UL)                    /*!< SCU PRER1: TIMER4 (Bit 20)                            */
#define SCU_PRER1_TIMER4_Msk              (0x100000UL)              /*!< SCU PRER1: TIMER4 (Bitfield-Mask: 0x01)               */
#define SCU_PRER1_TIMER3_Pos              (19UL)                    /*!< SCU PRER1: TIMER3 (Bit 19)                            */
#define SCU_PRER1_TIMER3_Msk              (0x80000UL)               /*!< SCU PRER1: TIMER3 (Bitfield-Mask: 0x01)               */
#define SCU_PRER1_TIMER2_Pos              (18UL)                    /*!< SCU PRER1: TIMER2 (Bit 18)                            */
#define SCU_PRER1_TIMER2_Msk              (0x40000UL)               /*!< SCU PRER1: TIMER2 (Bitfield-Mask: 0x01)               */
#define SCU_PRER1_TIMER1_Pos              (17UL)                    /*!< SCU PRER1: TIMER1 (Bit 17)                            */
#define SCU_PRER1_TIMER1_Msk              (0x20000UL)               /*!< SCU PRER1: TIMER1 (Bitfield-Mask: 0x01)               */
#define SCU_PRER1_TIMER0_Pos              (16UL)                    /*!< SCU PRER1: TIMER0 (Bit 16)                            */
#define SCU_PRER1_TIMER0_Msk              (0x10000UL)               /*!< SCU PRER1: TIMER0 (Bitfield-Mask: 0x01)               */
#define SCU_PRER1_GPIOG_Pos               (14UL)                    /*!< SCU PRER1: GPIOG (Bit 14)                             */
#define SCU_PRER1_GPIOG_Msk               (0x4000UL)                /*!< SCU PRER1: GPIOG (Bitfield-Mask: 0x01)                */
#define SCU_PRER1_GPIOF_Pos               (13UL)                    /*!< SCU PRER1: GPIOF (Bit 13)                             */
#define SCU_PRER1_GPIOF_Msk               (0x2000UL)                /*!< SCU PRER1: GPIOF (Bitfield-Mask: 0x01)                */
#define SCU_PRER1_GPIOE_Pos               (12UL)                    /*!< SCU PRER1: GPIOE (Bit 12)                             */
#define SCU_PRER1_GPIOE_Msk               (0x1000UL)                /*!< SCU PRER1: GPIOE (Bitfield-Mask: 0x01)                */
#define SCU_PRER1_GPIOD_Pos               (11UL)                    /*!< SCU PRER1: GPIOD (Bit 11)                             */
#define SCU_PRER1_GPIOD_Msk               (0x800UL)                 /*!< SCU PRER1: GPIOD (Bitfield-Mask: 0x01)                */
#define SCU_PRER1_GPIOC_Pos               (10UL)                    /*!< SCU PRER1: GPIOC (Bit 10)                             */
#define SCU_PRER1_GPIOC_Msk               (0x400UL)                 /*!< SCU PRER1: GPIOC (Bitfield-Mask: 0x01)                */
#define SCU_PRER1_GPIOB_Pos               (9UL)                     /*!< SCU PRER1: GPIOB (Bit 9)                              */
#define SCU_PRER1_GPIOB_Msk               (0x200UL)                 /*!< SCU PRER1: GPIOB (Bitfield-Mask: 0x01)                */
#define SCU_PRER1_GPIOA_Pos               (8UL)                     /*!< SCU PRER1: GPIOA (Bit 8)                              */
#define SCU_PRER1_GPIOA_Msk               (0x100UL)                 /*!< SCU PRER1: GPIOA (Bitfield-Mask: 0x01)                */
#define SCU_PRER1_FRT1_Pos                (7UL)                     /*!< SCU PRER1: FRT1 (Bit 7)                               */
#define SCU_PRER1_FRT1_Msk                (0x80UL)                  /*!< SCU PRER1: FRT1 (Bitfield-Mask: 0x01)                 */
#define SCU_PRER1_FRT0_Pos                (6UL)                     /*!< SCU PRER1: FRT0 (Bit 6)                               */
#define SCU_PRER1_FRT0_Msk                (0x40UL)                  /*!< SCU PRER1: FRT0 (Bitfield-Mask: 0x01)                 */
#define SCU_PRER1_DMA_Pos                 (4UL)                     /*!< SCU PRER1: DMA (Bit 4)                                */
#define SCU_PRER1_DMA_Msk                 (0x10UL)                  /*!< SCU PRER1: DMA (Bitfield-Mask: 0x01)                  */
/* =========================================================  PRER2  ========================================================= */
#define SCU_PRER2_RNG_Pos                 (31UL)                    /*!< SCU PRER2: RNG (Bit 31)                               */
#define SCU_PRER2_RNG_Msk                 (0x80000000UL)            /*!< SCU PRER2: RNG (Bitfield-Mask: 0x01)                  */
#define SCU_PRER2_AES_Pos                 (30UL)                    /*!< SCU PRER2: AES (Bit 30)                               */
#define SCU_PRER2_AES_Msk                 (0x40000000UL)            /*!< SCU PRER2: AES (Bitfield-Mask: 0x01)                  */
#define SCU_PRER2_CRC_Pos                 (29UL)                    /*!< SCU PRER2: CRC (Bit 29)                               */
#define SCU_PRER2_CRC_Msk                 (0x20000000UL)            /*!< SCU PRER2: CRC (Bitfield-Mask: 0x01)                  */
#define SCU_PRER2_COMPARATOR_Pos          (28UL)                    /*!< SCU PRER2: COMPARATOR (Bit 28)                        */
#define SCU_PRER2_COMPARATOR_Msk          (0x10000000UL)            /*!< SCU PRER2: COMPARATOR (Bitfield-Mask: 0x01)           */
#define SCU_PRER2_CAN_Pos                 (26UL)                    /*!< SCU PRER2: CAN (Bit 26)                               */
#define SCU_PRER2_CAN_Msk                 (0x4000000UL)             /*!< SCU PRER2: CAN (Bitfield-Mask: 0x01)                  */
#define SCU_PRER2_PGA_Pos                 (24UL)                    /*!< SCU PRER2: PGA (Bit 24)                               */
#define SCU_PRER2_PGA_Msk                 (0x1000000UL)             /*!< SCU PRER2: PGA (Bitfield-Mask: 0x01)                  */
#define SCU_PRER2_ADC2_Pos                (22UL)                    /*!< SCU PRER2: ADC2 (Bit 22)                              */
#define SCU_PRER2_ADC2_Msk                (0x400000UL)              /*!< SCU PRER2: ADC2 (Bitfield-Mask: 0x01)                 */
#define SCU_PRER2_ADC1_Pos                (21UL)                    /*!< SCU PRER2: ADC1 (Bit 21)                              */
#define SCU_PRER2_ADC1_Msk                (0x200000UL)              /*!< SCU PRER2: ADC1 (Bitfield-Mask: 0x01)                 */
#define SCU_PRER2_ADC0_Pos                (20UL)                    /*!< SCU PRER2: ADC0 (Bit 20)                              */
#define SCU_PRER2_ADC0_Msk                (0x100000UL)              /*!< SCU PRER2: ADC0 (Bitfield-Mask: 0x01)                 */
#define SCU_PRER2_MPWM1_Pos               (17UL)                    /*!< SCU PRER2: MPWM1 (Bit 17)                             */
#define SCU_PRER2_MPWM1_Msk               (0x20000UL)               /*!< SCU PRER2: MPWM1 (Bitfield-Mask: 0x01)                */
#define SCU_PRER2_MPWM0_Pos               (16UL)                    /*!< SCU PRER2: MPWM0 (Bit 16)                             */
#define SCU_PRER2_MPWM0_Msk               (0x10000UL)               /*!< SCU PRER2: MPWM0 (Bitfield-Mask: 0x01)                */
#define SCU_PRER2_UART5_Pos               (13UL)                    /*!< SCU PRER2: UART5 (Bit 13)                             */
#define SCU_PRER2_UART5_Msk               (0x2000UL)                /*!< SCU PRER2: UART5 (Bitfield-Mask: 0x01)                */
#define SCU_PRER2_UART4_Pos               (12UL)                    /*!< SCU PRER2: UART4 (Bit 12)                             */
#define SCU_PRER2_UART4_Msk               (0x1000UL)                /*!< SCU PRER2: UART4 (Bitfield-Mask: 0x01)                */
#define SCU_PRER2_UART3_Pos               (11UL)                    /*!< SCU PRER2: UART3 (Bit 11)                             */
#define SCU_PRER2_UART3_Msk               (0x800UL)                 /*!< SCU PRER2: UART3 (Bitfield-Mask: 0x01)                */
#define SCU_PRER2_UART2_Pos               (10UL)                    /*!< SCU PRER2: UART2 (Bit 10)                             */
#define SCU_PRER2_UART2_Msk               (0x400UL)                 /*!< SCU PRER2: UART2 (Bitfield-Mask: 0x01)                */
#define SCU_PRER2_UART1_Pos               (9UL)                     /*!< SCU PRER2: UART1 (Bit 9)                              */
#define SCU_PRER2_UART1_Msk               (0x200UL)                 /*!< SCU PRER2: UART1 (Bitfield-Mask: 0x01)                */
#define SCU_PRER2_UART0_Pos               (8UL)                     /*!< SCU PRER2: UART0 (Bit 8)                              */
#define SCU_PRER2_UART0_Msk               (0x100UL)                 /*!< SCU PRER2: UART0 (Bitfield-Mask: 0x01)                */
#define SCU_PRER2_I2C1_Pos                (5UL)                     /*!< SCU PRER2: I2C1 (Bit 5)                               */
#define SCU_PRER2_I2C1_Msk                (0x20UL)                  /*!< SCU PRER2: I2C1 (Bitfield-Mask: 0x01)                 */
#define SCU_PRER2_I2C0_Pos                (4UL)                     /*!< SCU PRER2: I2C0 (Bit 4)                               */
#define SCU_PRER2_I2C0_Msk                (0x10UL)                  /*!< SCU PRER2: I2C0 (Bitfield-Mask: 0x01)                 */
#define SCU_PRER2_SPI2_Pos                (2UL)                     /*!< SCU PRER2: SPI2 (Bit 2)                               */
#define SCU_PRER2_SPI2_Msk                (0x4UL)                   /*!< SCU PRER2: SPI2 (Bitfield-Mask: 0x01)                 */
#define SCU_PRER2_SPI1_Pos                (1UL)                     /*!< SCU PRER2: SPI1 (Bit 1)                               */
#define SCU_PRER2_SPI1_Msk                (0x2UL)                   /*!< SCU PRER2: SPI1 (Bitfield-Mask: 0x01)                 */
#define SCU_PRER2_SPI0_Pos                (0UL)                     /*!< SCU PRER2: SPI0 (Bit 0)                               */
#define SCU_PRER2_SPI0_Msk                (0x1UL)                   /*!< SCU PRER2: SPI0 (Bitfield-Mask: 0x01)                 */
/* =========================================================  PER1  ========================================================== */
#define SCU_PER1_QEI1_Pos                 (29UL)                    /*!< SCU PER1: QEI1 (Bit 29)                               */
#define SCU_PER1_QEI1_Msk                 (0x20000000UL)            /*!< SCU PER1: QEI1 (Bitfield-Mask: 0x01)                  */
#define SCU_PER1_QEI0_Pos                 (28UL)                    /*!< SCU PER1: QEI0 (Bit 28)                               */
#define SCU_PER1_QEI0_Msk                 (0x10000000UL)            /*!< SCU PER1: QEI0 (Bitfield-Mask: 0x01)                  */
#define SCU_PER1_TIMER9_Pos               (25UL)                    /*!< SCU PER1: TIMER9 (Bit 25)                             */
#define SCU_PER1_TIMER9_Msk               (0x2000000UL)             /*!< SCU PER1: TIMER9 (Bitfield-Mask: 0x01)                */
#define SCU_PER1_TIMER8_Pos               (24UL)                    /*!< SCU PER1: TIMER8 (Bit 24)                             */
#define SCU_PER1_TIMER8_Msk               (0x1000000UL)             /*!< SCU PER1: TIMER8 (Bitfield-Mask: 0x01)                */
#define SCU_PER1_TIMER7_Pos               (23UL)                    /*!< SCU PER1: TIMER7 (Bit 23)                             */
#define SCU_PER1_TIMER7_Msk               (0x800000UL)              /*!< SCU PER1: TIMER7 (Bitfield-Mask: 0x01)                */
#define SCU_PER1_TIMER6_Pos               (22UL)                    /*!< SCU PER1: TIMER6 (Bit 22)                             */
#define SCU_PER1_TIMER6_Msk               (0x400000UL)              /*!< SCU PER1: TIMER6 (Bitfield-Mask: 0x01)                */
#define SCU_PER1_TIMER5_Pos               (21UL)                    /*!< SCU PER1: TIMER5 (Bit 21)                             */
#define SCU_PER1_TIMER5_Msk               (0x200000UL)              /*!< SCU PER1: TIMER5 (Bitfield-Mask: 0x01)                */
#define SCU_PER1_TIMER4_Pos               (20UL)                    /*!< SCU PER1: TIMER4 (Bit 20)                             */
#define SCU_PER1_TIMER4_Msk               (0x100000UL)              /*!< SCU PER1: TIMER4 (Bitfield-Mask: 0x01)                */
#define SCU_PER1_TIMER3_Pos               (19UL)                    /*!< SCU PER1: TIMER3 (Bit 19)                             */
#define SCU_PER1_TIMER3_Msk               (0x80000UL)               /*!< SCU PER1: TIMER3 (Bitfield-Mask: 0x01)                */
#define SCU_PER1_TIMER2_Pos               (18UL)                    /*!< SCU PER1: TIMER2 (Bit 18)                             */
#define SCU_PER1_TIMER2_Msk               (0x40000UL)               /*!< SCU PER1: TIMER2 (Bitfield-Mask: 0x01)                */
#define SCU_PER1_TIMER1_Pos               (17UL)                    /*!< SCU PER1: TIMER1 (Bit 17)                             */
#define SCU_PER1_TIMER1_Msk               (0x20000UL)               /*!< SCU PER1: TIMER1 (Bitfield-Mask: 0x01)                */
#define SCU_PER1_TIMER0_Pos               (16UL)                    /*!< SCU PER1: TIMER0 (Bit 16)                             */
#define SCU_PER1_TIMER0_Msk               (0x10000UL)               /*!< SCU PER1: TIMER0 (Bitfield-Mask: 0x01)                */
#define SCU_PER1_GPIOG_Pos                (14UL)                    /*!< SCU PER1: GPIOG (Bit 14)                              */
#define SCU_PER1_GPIOG_Msk                (0x4000UL)                /*!< SCU PER1: GPIOG (Bitfield-Mask: 0x01)                 */
#define SCU_PER1_GPIOF_Pos                (13UL)                    /*!< SCU PER1: GPIOF (Bit 13)                              */
#define SCU_PER1_GPIOF_Msk                (0x2000UL)                /*!< SCU PER1: GPIOF (Bitfield-Mask: 0x01)                 */
#define SCU_PER1_GPIOE_Pos                (12UL)                    /*!< SCU PER1: GPIOE (Bit 12)                              */
#define SCU_PER1_GPIOE_Msk                (0x1000UL)                /*!< SCU PER1: GPIOE (Bitfield-Mask: 0x01)                 */
#define SCU_PER1_GPIOD_Pos                (11UL)                    /*!< SCU PER1: GPIOD (Bit 11)                              */
#define SCU_PER1_GPIOD_Msk                (0x800UL)                 /*!< SCU PER1: GPIOD (Bitfield-Mask: 0x01)                 */
#define SCU_PER1_GPIOC_Pos                (10UL)                    /*!< SCU PER1: GPIOC (Bit 10)                              */
#define SCU_PER1_GPIOC_Msk                (0x400UL)                 /*!< SCU PER1: GPIOC (Bitfield-Mask: 0x01)                 */
#define SCU_PER1_GPIOB_Pos                (9UL)                     /*!< SCU PER1: GPIOB (Bit 9)                               */
#define SCU_PER1_GPIOB_Msk                (0x200UL)                 /*!< SCU PER1: GPIOB (Bitfield-Mask: 0x01)                 */
#define SCU_PER1_GPIOA_Pos                (8UL)                     /*!< SCU PER1: GPIOA (Bit 8)                               */
#define SCU_PER1_GPIOA_Msk                (0x100UL)                 /*!< SCU PER1: GPIOA (Bitfield-Mask: 0x01)                 */
#define SCU_PER1_FRT1_Pos                 (7UL)                     /*!< SCU PER1: FRT1 (Bit 7)                                */
#define SCU_PER1_FRT1_Msk                 (0x80UL)                  /*!< SCU PER1: FRT1 (Bitfield-Mask: 0x01)                  */
#define SCU_PER1_FRT0_Pos                 (6UL)                     /*!< SCU PER1: FRT0 (Bit 6)                                */
#define SCU_PER1_FRT0_Msk                 (0x40UL)                  /*!< SCU PER1: FRT0 (Bitfield-Mask: 0x01)                  */
#define SCU_PER1_DMA_Pos                  (4UL)                     /*!< SCU PER1: DMA (Bit 4)                                 */
#define SCU_PER1_DMA_Msk                  (0x10UL)                  /*!< SCU PER1: DMA (Bitfield-Mask: 0x01)                   */
/* =========================================================  PER2  ========================================================== */
#define SCU_PER2_RNG_Pos                  (31UL)                    /*!< SCU PER2: RNG (Bit 31)                                */
#define SCU_PER2_RNG_Msk                  (0x80000000UL)            /*!< SCU PER2: RNG (Bitfield-Mask: 0x01)                   */
#define SCU_PER2_AES_Pos                  (30UL)                    /*!< SCU PER2: AES (Bit 30)                                */
#define SCU_PER2_AES_Msk                  (0x40000000UL)            /*!< SCU PER2: AES (Bitfield-Mask: 0x01)                   */
#define SCU_PER2_CRC_Pos                  (29UL)                    /*!< SCU PER2: CRC (Bit 29)                                */
#define SCU_PER2_CRC_Msk                  (0x20000000UL)            /*!< SCU PER2: CRC (Bitfield-Mask: 0x01)                   */
#define SCU_PER2_COMPARATOR_Pos           (28UL)                    /*!< SCU PER2: COMPARATOR (Bit 28)                         */
#define SCU_PER2_COMPARATOR_Msk           (0x10000000UL)            /*!< SCU PER2: COMPARATOR (Bitfield-Mask: 0x01)            */
#define SCU_PER2_CAN_Pos                  (26UL)                    /*!< SCU PER2: CAN (Bit 26)                                */
#define SCU_PER2_CAN_Msk                  (0x4000000UL)             /*!< SCU PER2: CAN (Bitfield-Mask: 0x01)                   */
#define SCU_PER2_PGA_Pos                  (24UL)                    /*!< SCU PER2: PGA (Bit 24)                                */
#define SCU_PER2_PGA_Msk                  (0x1000000UL)             /*!< SCU PER2: PGA (Bitfield-Mask: 0x01)                   */
#define SCU_PER2_ADC2_Pos                 (22UL)                    /*!< SCU PER2: ADC2 (Bit 22)                               */
#define SCU_PER2_ADC2_Msk                 (0x400000UL)              /*!< SCU PER2: ADC2 (Bitfield-Mask: 0x01)                  */
#define SCU_PER2_ADC1_Pos                 (21UL)                    /*!< SCU PER2: ADC1 (Bit 21)                               */
#define SCU_PER2_ADC1_Msk                 (0x200000UL)              /*!< SCU PER2: ADC1 (Bitfield-Mask: 0x01)                  */
#define SCU_PER2_ADC0_Pos                 (20UL)                    /*!< SCU PER2: ADC0 (Bit 20)                               */
#define SCU_PER2_ADC0_Msk                 (0x100000UL)              /*!< SCU PER2: ADC0 (Bitfield-Mask: 0x01)                  */
#define SCU_PER2_MPWM1_Pos                (17UL)                    /*!< SCU PER2: MPWM1 (Bit 17)                              */
#define SCU_PER2_MPWM1_Msk                (0x20000UL)               /*!< SCU PER2: MPWM1 (Bitfield-Mask: 0x01)                 */
#define SCU_PER2_MPWM0_Pos                (16UL)                    /*!< SCU PER2: MPWM0 (Bit 16)                              */
#define SCU_PER2_MPWM0_Msk                (0x10000UL)               /*!< SCU PER2: MPWM0 (Bitfield-Mask: 0x01)                 */
#define SCU_PER2_UART5_Pos                (13UL)                    /*!< SCU PER2: UART5 (Bit 13)                              */
#define SCU_PER2_UART5_Msk                (0x2000UL)                /*!< SCU PER2: UART5 (Bitfield-Mask: 0x01)                 */
#define SCU_PER2_UART4_Pos                (12UL)                    /*!< SCU PER2: UART4 (Bit 12)                              */
#define SCU_PER2_UART4_Msk                (0x1000UL)                /*!< SCU PER2: UART4 (Bitfield-Mask: 0x01)                 */
#define SCU_PER2_UART3_Pos                (11UL)                    /*!< SCU PER2: UART3 (Bit 11)                              */
#define SCU_PER2_UART3_Msk                (0x800UL)                 /*!< SCU PER2: UART3 (Bitfield-Mask: 0x01)                 */
#define SCU_PER2_UART2_Pos                (10UL)                    /*!< SCU PER2: UART2 (Bit 10)                              */
#define SCU_PER2_UART2_Msk                (0x400UL)                 /*!< SCU PER2: UART2 (Bitfield-Mask: 0x01)                 */
#define SCU_PER2_UART1_Pos                (9UL)                     /*!< SCU PER2: UART1 (Bit 9)                               */
#define SCU_PER2_UART1_Msk                (0x200UL)                 /*!< SCU PER2: UART1 (Bitfield-Mask: 0x01)                 */
#define SCU_PER2_UART0_Pos                (8UL)                     /*!< SCU PER2: UART0 (Bit 8)                               */
#define SCU_PER2_UART0_Msk                (0x100UL)                 /*!< SCU PER2: UART0 (Bitfield-Mask: 0x01)                 */
#define SCU_PER2_I2C1_Pos                 (5UL)                     /*!< SCU PER2: I2C1 (Bit 5)                                */
#define SCU_PER2_I2C1_Msk                 (0x20UL)                  /*!< SCU PER2: I2C1 (Bitfield-Mask: 0x01)                  */
#define SCU_PER2_I2C0_Pos                 (4UL)                     /*!< SCU PER2: I2C0 (Bit 4)                                */
#define SCU_PER2_I2C0_Msk                 (0x10UL)                  /*!< SCU PER2: I2C0 (Bitfield-Mask: 0x01)                  */
#define SCU_PER2_SPI2_Pos                 (2UL)                     /*!< SCU PER2: SPI2 (Bit 2)                                */
#define SCU_PER2_SPI2_Msk                 (0x4UL)                   /*!< SCU PER2: SPI2 (Bitfield-Mask: 0x01)                  */
#define SCU_PER2_SPI1_Pos                 (1UL)                     /*!< SCU PER2: SPI1 (Bit 1)                                */
#define SCU_PER2_SPI1_Msk                 (0x2UL)                   /*!< SCU PER2: SPI1 (Bitfield-Mask: 0x01)                  */
#define SCU_PER2_SPI0_Pos                 (0UL)                     /*!< SCU PER2: SPI0 (Bit 0)                                */
#define SCU_PER2_SPI0_Msk                 (0x1UL)                   /*!< SCU PER2: SPI0 (Bitfield-Mask: 0x01)                  */
/* =========================================================  PCER1  ========================================================= */
#define SCU_PCER1_QEI1_Pos                (29UL)                    /*!< SCU PCER1: QEI1 (Bit 29)                              */
#define SCU_PCER1_QEI1_Msk                (0x20000000UL)            /*!< SCU PCER1: QEI1 (Bitfield-Mask: 0x01)                 */
#define SCU_PCER1_QEI0_Pos                (28UL)                    /*!< SCU PCER1: QEI0 (Bit 28)                              */
#define SCU_PCER1_QEI0_Msk                (0x10000000UL)            /*!< SCU PCER1: QEI0 (Bitfield-Mask: 0x01)                 */
#define SCU_PCER1_TIMER9_Pos              (25UL)                    /*!< SCU PCER1: TIMER9 (Bit 25)                            */
#define SCU_PCER1_TIMER9_Msk              (0x2000000UL)             /*!< SCU PCER1: TIMER9 (Bitfield-Mask: 0x01)               */
#define SCU_PCER1_TIMER8_Pos              (24UL)                    /*!< SCU PCER1: TIMER8 (Bit 24)                            */
#define SCU_PCER1_TIMER8_Msk              (0x1000000UL)             /*!< SCU PCER1: TIMER8 (Bitfield-Mask: 0x01)               */
#define SCU_PCER1_TIMER7_Pos              (23UL)                    /*!< SCU PCER1: TIMER7 (Bit 23)                            */
#define SCU_PCER1_TIMER7_Msk              (0x800000UL)              /*!< SCU PCER1: TIMER7 (Bitfield-Mask: 0x01)               */
#define SCU_PCER1_TIMER6_Pos              (22UL)                    /*!< SCU PCER1: TIMER6 (Bit 22)                            */
#define SCU_PCER1_TIMER6_Msk              (0x400000UL)              /*!< SCU PCER1: TIMER6 (Bitfield-Mask: 0x01)               */
#define SCU_PCER1_TIMER5_Pos              (21UL)                    /*!< SCU PCER1: TIMER5 (Bit 21)                            */
#define SCU_PCER1_TIMER5_Msk              (0x200000UL)              /*!< SCU PCER1: TIMER5 (Bitfield-Mask: 0x01)               */
#define SCU_PCER1_TIMER4_Pos              (20UL)                    /*!< SCU PCER1: TIMER4 (Bit 20)                            */
#define SCU_PCER1_TIMER4_Msk              (0x100000UL)              /*!< SCU PCER1: TIMER4 (Bitfield-Mask: 0x01)               */
#define SCU_PCER1_TIMER3_Pos              (19UL)                    /*!< SCU PCER1: TIMER3 (Bit 19)                            */
#define SCU_PCER1_TIMER3_Msk              (0x80000UL)               /*!< SCU PCER1: TIMER3 (Bitfield-Mask: 0x01)               */
#define SCU_PCER1_TIMER2_Pos              (18UL)                    /*!< SCU PCER1: TIMER2 (Bit 18)                            */
#define SCU_PCER1_TIMER2_Msk              (0x40000UL)               /*!< SCU PCER1: TIMER2 (Bitfield-Mask: 0x01)               */
#define SCU_PCER1_TIMER1_Pos              (17UL)                    /*!< SCU PCER1: TIMER1 (Bit 17)                            */
#define SCU_PCER1_TIMER1_Msk              (0x20000UL)               /*!< SCU PCER1: TIMER1 (Bitfield-Mask: 0x01)               */
#define SCU_PCER1_TIMER0_Pos              (16UL)                    /*!< SCU PCER1: TIMER0 (Bit 16)                            */
#define SCU_PCER1_TIMER0_Msk              (0x10000UL)               /*!< SCU PCER1: TIMER0 (Bitfield-Mask: 0x01)               */
#define SCU_PCER1_GPIOG_Pos               (14UL)                    /*!< SCU PCER1: GPIOG (Bit 14)                             */
#define SCU_PCER1_GPIOG_Msk               (0x4000UL)                /*!< SCU PCER1: GPIOG (Bitfield-Mask: 0x01)                */
#define SCU_PCER1_GPIOF_Pos               (13UL)                    /*!< SCU PCER1: GPIOF (Bit 13)                             */
#define SCU_PCER1_GPIOF_Msk               (0x2000UL)                /*!< SCU PCER1: GPIOF (Bitfield-Mask: 0x01)                */
#define SCU_PCER1_GPIOE_Pos               (12UL)                    /*!< SCU PCER1: GPIOE (Bit 12)                             */
#define SCU_PCER1_GPIOE_Msk               (0x1000UL)                /*!< SCU PCER1: GPIOE (Bitfield-Mask: 0x01)                */
#define SCU_PCER1_GPIOD_Pos               (11UL)                    /*!< SCU PCER1: GPIOD (Bit 11)                             */
#define SCU_PCER1_GPIOD_Msk               (0x800UL)                 /*!< SCU PCER1: GPIOD (Bitfield-Mask: 0x01)                */
#define SCU_PCER1_GPIOC_Pos               (10UL)                    /*!< SCU PCER1: GPIOC (Bit 10)                             */
#define SCU_PCER1_GPIOC_Msk               (0x400UL)                 /*!< SCU PCER1: GPIOC (Bitfield-Mask: 0x01)                */
#define SCU_PCER1_GPIOB_Pos               (9UL)                     /*!< SCU PCER1: GPIOB (Bit 9)                              */
#define SCU_PCER1_GPIOB_Msk               (0x200UL)                 /*!< SCU PCER1: GPIOB (Bitfield-Mask: 0x01)                */
#define SCU_PCER1_GPIOA_Pos               (8UL)                     /*!< SCU PCER1: GPIOA (Bit 8)                              */
#define SCU_PCER1_GPIOA_Msk               (0x100UL)                 /*!< SCU PCER1: GPIOA (Bitfield-Mask: 0x01)                */
#define SCU_PCER1_FRT1_Pos                (7UL)                     /*!< SCU PCER1: FRT1 (Bit 7)                               */
#define SCU_PCER1_FRT1_Msk                (0x80UL)                  /*!< SCU PCER1: FRT1 (Bitfield-Mask: 0x01)                 */
#define SCU_PCER1_FRT0_Pos                (6UL)                     /*!< SCU PCER1: FRT0 (Bit 6)                               */
#define SCU_PCER1_FRT0_Msk                (0x40UL)                  /*!< SCU PCER1: FRT0 (Bitfield-Mask: 0x01)                 */
#define SCU_PCER1_DMA_Pos                 (4UL)                     /*!< SCU PCER1: DMA (Bit 4)                                */
#define SCU_PCER1_DMA_Msk                 (0x10UL)                  /*!< SCU PCER1: DMA (Bitfield-Mask: 0x01)                  */
/* =========================================================  PCER2  ========================================================= */
#define SCU_PCER2_RNG_Pos                 (31UL)                    /*!< SCU PCER2: RNG (Bit 31)                               */
#define SCU_PCER2_RNG_Msk                 (0x80000000UL)            /*!< SCU PCER2: RNG (Bitfield-Mask: 0x01)                  */
#define SCU_PCER2_AES_Pos                 (30UL)                    /*!< SCU PCER2: AES (Bit 30)                               */
#define SCU_PCER2_AES_Msk                 (0x40000000UL)            /*!< SCU PCER2: AES (Bitfield-Mask: 0x01)                  */
#define SCU_PCER2_CRC_Pos                 (29UL)                    /*!< SCU PCER2: CRC (Bit 29)                               */
#define SCU_PCER2_CRC_Msk                 (0x20000000UL)            /*!< SCU PCER2: CRC (Bitfield-Mask: 0x01)                  */
#define SCU_PCER2_COMPARATOR_Pos          (28UL)                    /*!< SCU PCER2: COMPARATOR (Bit 28)                        */
#define SCU_PCER2_COMPARATOR_Msk          (0x10000000UL)            /*!< SCU PCER2: COMPARATOR (Bitfield-Mask: 0x01)           */
#define SCU_PCER2_CAN_Pos                 (26UL)                    /*!< SCU PCER2: CAN (Bit 26)                               */
#define SCU_PCER2_CAN_Msk                 (0x4000000UL)             /*!< SCU PCER2: CAN (Bitfield-Mask: 0x01)                  */
#define SCU_PCER2_PGA_Pos                 (24UL)                    /*!< SCU PCER2: PGA (Bit 24)                               */
#define SCU_PCER2_PGA_Msk                 (0x1000000UL)             /*!< SCU PCER2: PGA (Bitfield-Mask: 0x01)                  */
#define SCU_PCER2_ADC2_Pos                (22UL)                    /*!< SCU PCER2: ADC2 (Bit 22)                              */
#define SCU_PCER2_ADC2_Msk                (0x400000UL)              /*!< SCU PCER2: ADC2 (Bitfield-Mask: 0x01)                 */
#define SCU_PCER2_ADC1_Pos                (21UL)                    /*!< SCU PCER2: ADC1 (Bit 21)                              */
#define SCU_PCER2_ADC1_Msk                (0x200000UL)              /*!< SCU PCER2: ADC1 (Bitfield-Mask: 0x01)                 */
#define SCU_PCER2_ADC0_Pos                (20UL)                    /*!< SCU PCER2: ADC0 (Bit 20)                              */
#define SCU_PCER2_ADC0_Msk                (0x100000UL)              /*!< SCU PCER2: ADC0 (Bitfield-Mask: 0x01)                 */
#define SCU_PCER2_MPWM1_Pos               (17UL)                    /*!< SCU PCER2: MPWM1 (Bit 17)                             */
#define SCU_PCER2_MPWM1_Msk               (0x20000UL)               /*!< SCU PCER2: MPWM1 (Bitfield-Mask: 0x01)                */
#define SCU_PCER2_MPWM0_Pos               (16UL)                    /*!< SCU PCER2: MPWM0 (Bit 16)                             */
#define SCU_PCER2_MPWM0_Msk               (0x10000UL)               /*!< SCU PCER2: MPWM0 (Bitfield-Mask: 0x01)                */
#define SCU_PCER2_UART5_Pos               (13UL)                    /*!< SCU PCER2: UART5 (Bit 13)                             */
#define SCU_PCER2_UART5_Msk               (0x2000UL)                /*!< SCU PCER2: UART5 (Bitfield-Mask: 0x01)                */
#define SCU_PCER2_UART4_Pos               (12UL)                    /*!< SCU PCER2: UART4 (Bit 12)                             */
#define SCU_PCER2_UART4_Msk               (0x1000UL)                /*!< SCU PCER2: UART4 (Bitfield-Mask: 0x01)                */
#define SCU_PCER2_UART3_Pos               (11UL)                    /*!< SCU PCER2: UART3 (Bit 11)                             */
#define SCU_PCER2_UART3_Msk               (0x800UL)                 /*!< SCU PCER2: UART3 (Bitfield-Mask: 0x01)                */
#define SCU_PCER2_UART2_Pos               (10UL)                    /*!< SCU PCER2: UART2 (Bit 10)                             */
#define SCU_PCER2_UART2_Msk               (0x400UL)                 /*!< SCU PCER2: UART2 (Bitfield-Mask: 0x01)                */
#define SCU_PCER2_UART1_Pos               (9UL)                     /*!< SCU PCER2: UART1 (Bit 9)                              */
#define SCU_PCER2_UART1_Msk               (0x200UL)                 /*!< SCU PCER2: UART1 (Bitfield-Mask: 0x01)                */
#define SCU_PCER2_UART0_Pos               (8UL)                     /*!< SCU PCER2: UART0 (Bit 8)                              */
#define SCU_PCER2_UART0_Msk               (0x100UL)                 /*!< SCU PCER2: UART0 (Bitfield-Mask: 0x01)                */
#define SCU_PCER2_I2C1_Pos                (5UL)                     /*!< SCU PCER2: I2C1 (Bit 5)                               */
#define SCU_PCER2_I2C1_Msk                (0x20UL)                  /*!< SCU PCER2: I2C1 (Bitfield-Mask: 0x01)                 */
#define SCU_PCER2_I2C0_Pos                (4UL)                     /*!< SCU PCER2: I2C0 (Bit 4)                               */
#define SCU_PCER2_I2C0_Msk                (0x10UL)                  /*!< SCU PCER2: I2C0 (Bitfield-Mask: 0x01)                 */
#define SCU_PCER2_SPI2_Pos                (2UL)                     /*!< SCU PCER2: SPI2 (Bit 2)                               */
#define SCU_PCER2_SPI2_Msk                (0x4UL)                   /*!< SCU PCER2: SPI2 (Bitfield-Mask: 0x01)                 */
#define SCU_PCER2_SPI1_Pos                (1UL)                     /*!< SCU PCER2: SPI1 (Bit 1)                               */
#define SCU_PCER2_SPI1_Msk                (0x2UL)                   /*!< SCU PCER2: SPI1 (Bitfield-Mask: 0x01)                 */
#define SCU_PCER2_SPI0_Pos                (0UL)                     /*!< SCU PCER2: SPI0 (Bit 0)                               */
#define SCU_PCER2_SPI0_Msk                (0x1UL)                   /*!< SCU PCER2: SPI0 (Bitfield-Mask: 0x01)                 */
/* =========================================================  CSCR  ========================================================== */
#define SCU_CSCR_LSECON_Pos               (7UL)                     /*!< SCU CSCR: LSECON (Bit 7)                              */
#define SCU_CSCR_LSECON_Msk               (0x80UL)                  /*!< SCU CSCR: LSECON (Bitfield-Mask: 0x01)                */
#define SCU_CSCR_LSICON_Pos               (5UL)                     /*!< SCU CSCR: LSICON (Bit 5)                              */
#define SCU_CSCR_LSICON_Msk               (0x20UL)                  /*!< SCU CSCR: LSICON (Bitfield-Mask: 0x01)                */
#define SCU_CSCR_HSICON_Pos               (3UL)                     /*!< SCU CSCR: HSICON (Bit 3)                              */
#define SCU_CSCR_HSICON_Msk               (0x8UL)                   /*!< SCU CSCR: HSICON (Bitfield-Mask: 0x01)                */
#define SCU_CSCR_HSECON_Pos               (1UL)                     /*!< SCU CSCR: HSECON (Bit 1)                              */
#define SCU_CSCR_HSECON_Msk               (0x2UL)                   /*!< SCU CSCR: HSECON (Bitfield-Mask: 0x01)                */
/* =========================================================  SCCR  ========================================================== */
#define SCU_SCCR_HCLKDIV_Pos              (24UL)                    /*!< SCU SCCR: HCLKDIV (Bit 24)                            */
#define SCU_SCCR_HCLKDIV_Msk              (0xf000000UL)             /*!< SCU SCCR: HCLKDIV (Bitfield-Mask: 0x0f)               */
#define SCU_SCCR_PCLKDIV_Pos              (16UL)                    /*!< SCU SCCR: PCLKDIV (Bit 16)                            */
#define SCU_SCCR_PCLKDIV_Msk              (0x70000UL)               /*!< SCU SCCR: PCLKDIV (Bitfield-Mask: 0x07)               */
#define SCU_SCCR_PLLCLKSEL_Pos            (12UL)                    /*!< SCU SCCR: PLLCLKSEL (Bit 12)                          */
#define SCU_SCCR_PLLCLKSEL_Msk            (0x1000UL)                /*!< SCU SCCR: PLLCLKSEL (Bitfield-Mask: 0x01)             */
#define SCU_SCCR_PLLPREDIV_Pos            (8UL)                     /*!< SCU SCCR: PLLPREDIV (Bit 8)                           */
#define SCU_SCCR_PLLPREDIV_Msk            (0x300UL)                 /*!< SCU SCCR: PLLPREDIV (Bitfield-Mask: 0x03)             */
#define SCU_SCCR_MCLKSEL_Pos              (0UL)                     /*!< SCU SCCR: MCLKSEL (Bit 0)                             */
#define SCU_SCCR_MCLKSEL_Msk              (0x7UL)                   /*!< SCU SCCR: MCLKSEL (Bitfield-Mask: 0x07)               */
/* ==========================================================  CMR  ========================================================== */
#define SCU_CMR_MCLKREC_Pos               (15UL)                    /*!< SCU CMR: MCLKREC (Bit 15)                             */
#define SCU_CMR_MCLKREC_Msk               (0x8000UL)                /*!< SCU CMR: MCLKREC (Bitfield-Mask: 0x01)                */
#define SCU_CMR_LSEMNT_Pos                (11UL)                    /*!< SCU CMR: LSEMNT (Bit 11)                              */
#define SCU_CMR_LSEMNT_Msk                (0x800UL)                 /*!< SCU CMR: LSEMNT (Bitfield-Mask: 0x01)                 */
#define SCU_CMR_LSEIE_Pos                 (10UL)                    /*!< SCU CMR: LSEIE (Bit 10)                               */
#define SCU_CMR_LSEIE_Msk                 (0x400UL)                 /*!< SCU CMR: LSEIE (Bitfield-Mask: 0x01)                  */
#define SCU_CMR_LSEFAIL_Pos               (9UL)                     /*!< SCU CMR: LSEFAIL (Bit 9)                              */
#define SCU_CMR_LSEFAIL_Msk               (0x200UL)                 /*!< SCU CMR: LSEFAIL (Bitfield-Mask: 0x01)                */
#define SCU_CMR_LSESTS_Pos                (8UL)                     /*!< SCU CMR: LSESTS (Bit 8)                               */
#define SCU_CMR_LSESTS_Msk                (0x100UL)                 /*!< SCU CMR: LSESTS (Bitfield-Mask: 0x01)                 */
#define SCU_CMR_MCLKMNT_Pos               (7UL)                     /*!< SCU CMR: MCLKMNT (Bit 7)                              */
#define SCU_CMR_MCLKMNT_Msk               (0x80UL)                  /*!< SCU CMR: MCLKMNT (Bitfield-Mask: 0x01)                */
#define SCU_CMR_MCLKIE_Pos                (6UL)                     /*!< SCU CMR: MCLKIE (Bit 6)                               */
#define SCU_CMR_MCLKIE_Msk                (0x40UL)                  /*!< SCU CMR: MCLKIE (Bitfield-Mask: 0x01)                 */
#define SCU_CMR_MCLKFAIL_Pos              (5UL)                     /*!< SCU CMR: MCLKFAIL (Bit 5)                             */
#define SCU_CMR_MCLKFAIL_Msk              (0x20UL)                  /*!< SCU CMR: MCLKFAIL (Bitfield-Mask: 0x01)               */
#define SCU_CMR_MCLKSTS_Pos               (4UL)                     /*!< SCU CMR: MCLKSTS (Bit 4)                              */
#define SCU_CMR_MCLKSTS_Msk               (0x10UL)                  /*!< SCU CMR: MCLKSTS (Bitfield-Mask: 0x01)                */
#define SCU_CMR_HSEMNT_Pos                (3UL)                     /*!< SCU CMR: HSEMNT (Bit 3)                               */
#define SCU_CMR_HSEMNT_Msk                (0x8UL)                   /*!< SCU CMR: HSEMNT (Bitfield-Mask: 0x01)                 */
#define SCU_CMR_HSEIE_Pos                 (2UL)                     /*!< SCU CMR: HSEIE (Bit 2)                                */
#define SCU_CMR_HSEIE_Msk                 (0x4UL)                   /*!< SCU CMR: HSEIE (Bitfield-Mask: 0x01)                  */
#define SCU_CMR_HSEFAIL_Pos               (1UL)                     /*!< SCU CMR: HSEFAIL (Bit 1)                              */
#define SCU_CMR_HSEFAIL_Msk               (0x2UL)                   /*!< SCU CMR: HSEFAIL (Bitfield-Mask: 0x01)                */
#define SCU_CMR_HSESTS_Pos                (0UL)                     /*!< SCU CMR: HSESTS (Bit 0)                               */
#define SCU_CMR_HSESTS_Msk                (0x1UL)                   /*!< SCU CMR: HSESTS (Bitfield-Mask: 0x01)                 */
/* ==========================================================  COR  ========================================================== */
#define SCU_COR_CLKOINSEL_Pos             (5UL)                     /*!< SCU COR: CLKOINSEL (Bit 5)                            */
#define SCU_COR_CLKOINSEL_Msk             (0xe0UL)                  /*!< SCU COR: CLKOINSEL (Bitfield-Mask: 0x07)              */
#define SCU_COR_CLKOEN_Pos                (4UL)                     /*!< SCU COR: CLKOEN (Bit 4)                               */
#define SCU_COR_CLKOEN_Msk                (0x10UL)                  /*!< SCU COR: CLKOEN (Bitfield-Mask: 0x01)                 */
#define SCU_COR_CLKODIV_Pos               (0UL)                     /*!< SCU COR: CLKODIV (Bit 0)                              */
#define SCU_COR_CLKODIV_Msk               (0xfUL)                   /*!< SCU COR: CLKODIV (Bitfield-Mask: 0x0f)                */
/* =========================================================  NMICR  ========================================================= */
#define SCU_NMICR_NMISRC_Pos              (16UL)                    /*!< SCU NMICR: NMISRC (Bit 16)                            */
#define SCU_NMICR_NMISRC_Msk              (0xff0000UL)              /*!< SCU NMICR: NMISRC (Bitfield-Mask: 0xff)               */
#define SCU_NMICR_NMIINEN_Pos             (15UL)                    /*!< SCU NMICR: NMIINEN (Bit 15)                           */
#define SCU_NMICR_NMIINEN_Msk             (0x8000UL)                /*!< SCU NMICR: NMIINEN (Bitfield-Mask: 0x01)              */
#define SCU_NMICR_PROT1EN_Pos             (6UL)                     /*!< SCU NMICR: PROT1EN (Bit 6)                            */
#define SCU_NMICR_PROT1EN_Msk             (0x40UL)                  /*!< SCU NMICR: PROT1EN (Bitfield-Mask: 0x01)              */
#define SCU_NMICR_OVP1EN_Pos              (5UL)                     /*!< SCU NMICR: OVP1EN (Bit 5)                             */
#define SCU_NMICR_OVP1EN_Msk              (0x20UL)                  /*!< SCU NMICR: OVP1EN (Bitfield-Mask: 0x01)               */
#define SCU_NMICR_PROT0EN_Pos             (4UL)                     /*!< SCU NMICR: PROT0EN (Bit 4)                            */
#define SCU_NMICR_PROT0EN_Msk             (0x10UL)                  /*!< SCU NMICR: PROT0EN (Bitfield-Mask: 0x01)              */
#define SCU_NMICR_OVP0EN_Pos              (3UL)                     /*!< SCU NMICR: OVP0EN (Bit 3)                             */
#define SCU_NMICR_OVP0EN_Msk              (0x8UL)                   /*!< SCU NMICR: OVP0EN (Bitfield-Mask: 0x01)               */
#define SCU_NMICR_WDTINTEN_Pos            (2UL)                     /*!< SCU NMICR: WDTINTEN (Bit 2)                           */
#define SCU_NMICR_WDTINTEN_Msk            (0x4UL)                   /*!< SCU NMICR: WDTINTEN (Bitfield-Mask: 0x01)             */
#define SCU_NMICR_MCLKFAILEN_Pos          (1UL)                     /*!< SCU NMICR: MCLKFAILEN (Bit 1)                         */
#define SCU_NMICR_MCLKFAILEN_Msk          (0x2UL)                   /*!< SCU NMICR: MCLKFAILEN (Bitfield-Mask: 0x01)           */
#define SCU_NMICR_LVDEN_Pos               (0UL)                     /*!< SCU NMICR: LVDEN (Bit 0)                              */
#define SCU_NMICR_LVDEN_Msk               (0x1UL)                   /*!< SCU NMICR: LVDEN (Bitfield-Mask: 0x01)                */
/* =========================================================  NMISR  ========================================================= */
#define SCU_NMISR_WTIDKY_Pos              (24UL)                    /*!< SCU NMISR: WTIDKY (Bit 24)                            */
#define SCU_NMISR_WTIDKY_Msk              (0xff000000UL)            /*!< SCU NMISR: WTIDKY (Bitfield-Mask: 0xff)               */
#define SCU_NMISR_NMIINTSTS_Pos           (15UL)                    /*!< SCU NMISR: NMIINTSTS (Bit 15)                         */
#define SCU_NMISR_NMIINTSTS_Msk           (0x8000UL)                /*!< SCU NMISR: NMIINTSTS (Bitfield-Mask: 0x01)            */
#define SCU_NMISR_PROT1STS_Pos            (6UL)                     /*!< SCU NMISR: PROT1STS (Bit 6)                           */
#define SCU_NMISR_PROT1STS_Msk            (0x40UL)                  /*!< SCU NMISR: PROT1STS (Bitfield-Mask: 0x01)             */
#define SCU_NMISR_OVP1STS_Pos             (5UL)                     /*!< SCU NMISR: OVP1STS (Bit 5)                            */
#define SCU_NMISR_OVP1STS_Msk             (0x20UL)                  /*!< SCU NMISR: OVP1STS (Bitfield-Mask: 0x01)              */
#define SCU_NMISR_PROT0STS_Pos            (4UL)                     /*!< SCU NMISR: PROT0STS (Bit 4)                           */
#define SCU_NMISR_PROT0STS_Msk            (0x10UL)                  /*!< SCU NMISR: PROT0STS (Bitfield-Mask: 0x01)             */
#define SCU_NMISR_OVP0STS_Pos             (3UL)                     /*!< SCU NMISR: OVP0STS (Bit 3)                            */
#define SCU_NMISR_OVP0STS_Msk             (0x8UL)                   /*!< SCU NMISR: OVP0STS (Bitfield-Mask: 0x01)              */
#define SCU_NMISR_WDTINTSTS_Pos           (2UL)                     /*!< SCU NMISR: WDTINTSTS (Bit 2)                          */
#define SCU_NMISR_WDTINTSTS_Msk           (0x4UL)                   /*!< SCU NMISR: WDTINTSTS (Bitfield-Mask: 0x01)            */
#define SCU_NMISR_MCLKFAILSTS_Pos         (1UL)                     /*!< SCU NMISR: MCLKFAILSTS (Bit 1)                        */
#define SCU_NMISR_MCLKFAILSTS_Msk         (0x2UL)                   /*!< SCU NMISR: MCLKFAILSTS (Bitfield-Mask: 0x01)          */
#define SCU_NMISR_LVDSTS_Pos              (0UL)                     /*!< SCU NMISR: LVDSTS (Bit 0)                             */
#define SCU_NMISR_LVDSTS_Msk              (0x1UL)                   /*!< SCU NMISR: LVDSTS (Bitfield-Mask: 0x01)               */
/* ========================================================  PLLCON  ========================================================= */
#define SCU_PLLCON_LOCKSTS_Pos            (31UL)                    /*!< SCU PLLCON: LOCKSTS (Bit 31)                          */
#define SCU_PLLCON_LOCKSTS_Msk            (0x80000000UL)            /*!< SCU PLLCON: LOCKSTS (Bitfield-Mask: 0x01)             */
#define SCU_PLLCON_PLLICP_Pos             (26UL)                    /*!< SCU PLLCON: PLLICP (Bit 26)                           */
#define SCU_PLLCON_PLLICP_Msk             (0xc000000UL)             /*!< SCU PLLCON: PLLICP (Bitfield-Mask: 0x03)              */
#define SCU_PLLCON_PLLVCOC_Pos            (24UL)                    /*!< SCU PLLCON: PLLVCOC (Bit 24)                          */
#define SCU_PLLCON_PLLVCOC_Msk            (0x3000000UL)             /*!< SCU PLLCON: PLLVCOC (Bitfield-Mask: 0x03)             */
#define SCU_PLLCON_PLLRSTB_Pos            (23UL)                    /*!< SCU PLLCON: PLLRSTB (Bit 23)                          */
#define SCU_PLLCON_PLLRSTB_Msk            (0x800000UL)              /*!< SCU PLLCON: PLLRSTB (Bitfield-Mask: 0x01)             */
#define SCU_PLLCON_PLLEN_Pos              (22UL)                    /*!< SCU PLLCON: PLLEN (Bit 22)                            */
#define SCU_PLLCON_PLLEN_Msk              (0x400000UL)              /*!< SCU PLLCON: PLLEN (Bitfield-Mask: 0x01)               */
#define SCU_PLLCON_BYPASSB_Pos            (21UL)                    /*!< SCU PLLCON: BYPASSB (Bit 21)                          */
#define SCU_PLLCON_BYPASSB_Msk            (0x200000UL)              /*!< SCU PLLCON: BYPASSB (Bitfield-Mask: 0x01)             */
#define SCU_PLLCON_PLLMODE_Pos            (20UL)                    /*!< SCU PLLCON: PLLMODE (Bit 20)                          */
#define SCU_PLLCON_PLLMODE_Msk            (0x100000UL)              /*!< SCU PLLCON: PLLMODE (Bitfield-Mask: 0x01)             */
#define SCU_PLLCON_PREDIV_Pos             (16UL)                    /*!< SCU PLLCON: PREDIV (Bit 16)                           */
#define SCU_PLLCON_PREDIV_Msk             (0x70000UL)               /*!< SCU PLLCON: PREDIV (Bitfield-Mask: 0x07)              */
#define SCU_PLLCON_POSTDIV1_Pos           (8UL)                     /*!< SCU PLLCON: POSTDIV1 (Bit 8)                          */
#define SCU_PLLCON_POSTDIV1_Msk           (0xff00UL)                /*!< SCU PLLCON: POSTDIV1 (Bitfield-Mask: 0xff)            */
#define SCU_PLLCON_POSTDIV2_Pos           (4UL)                     /*!< SCU PLLCON: POSTDIV2 (Bit 4)                          */
#define SCU_PLLCON_POSTDIV2_Msk           (0xf0UL)                  /*!< SCU PLLCON: POSTDIV2 (Bitfield-Mask: 0x0f)            */
#define SCU_PLLCON_OUTDIV_Pos             (0UL)                     /*!< SCU PLLCON: OUTDIV (Bit 0)                            */
#define SCU_PLLCON_OUTDIV_Msk             (0xfUL)                   /*!< SCU PLLCON: OUTDIV (Bitfield-Mask: 0x0f)              */
/* ========================================================  VDCCON  ========================================================= */
#define SCU_VDCCON_VDCWDLY_Pos            (0UL)                     /*!< SCU VDCCON: VDCWDLY (Bit 0)                           */
#define SCU_VDCCON_VDCWDLY_Msk            (0xffUL)                  /*!< SCU VDCCON: VDCWDLY (Bitfield-Mask: 0xff)             */
/* =========================================================  LVICR  ========================================================= */
#define SCU_LVICR_LVIEN_Pos               (7UL)                     /*!< SCU LVICR: LVIEN (Bit 7)                              */
#define SCU_LVICR_LVIEN_Msk               (0x80UL)                  /*!< SCU LVICR: LVIEN (Bitfield-Mask: 0x01)                */
#define SCU_LVICR_LVIINTEN_Pos            (5UL)                     /*!< SCU LVICR: LVIINTEN (Bit 5)                           */
#define SCU_LVICR_LVIINTEN_Msk            (0x20UL)                  /*!< SCU LVICR: LVIINTEN (Bitfield-Mask: 0x01)             */
#define SCU_LVICR_LVIAON_Pos              (4UL)                     /*!< SCU LVICR: LVIAON (Bit 4)                             */
#define SCU_LVICR_LVIAON_Msk              (0x10UL)                  /*!< SCU LVICR: LVIAON (Bitfield-Mask: 0x01)               */
#define SCU_LVICR_LVIVS_Pos               (0UL)                     /*!< SCU LVICR: LVIVS (Bit 0)                              */
#define SCU_LVICR_LVIVS_Msk               (0xfUL)                   /*!< SCU LVICR: LVIVS (Bitfield-Mask: 0x0f)                */
/* =========================================================  LVISR  ========================================================= */
#define SCU_LVISR_WTIDKY_Pos              (24UL)                    /*!< SCU LVISR: WTIDKY (Bit 24)                            */
#define SCU_LVISR_WTIDKY_Msk              (0xff000000UL)            /*!< SCU LVISR: WTIDKY (Bitfield-Mask: 0xff)               */
#define SCU_LVISR_LVIIFLAG_Pos            (5UL)                     /*!< SCU LVISR: LVIIFLAG (Bit 5)                           */
#define SCU_LVISR_LVIIFLAG_Msk            (0x20UL)                  /*!< SCU LVISR: LVIIFLAG (Bitfield-Mask: 0x01)             */
#define SCU_LVISR_LVIINTSTS_Pos           (0UL)                     /*!< SCU LVISR: LVIINTSTS (Bit 0)                          */
#define SCU_LVISR_LVIINTSTS_Msk           (0x1UL)                   /*!< SCU LVISR: LVIINTSTS (Bitfield-Mask: 0x01)            */
/* =========================================================  LVRCR  ========================================================= */
#define SCU_LVRCR_LVREN_Pos               (8UL)                     /*!< SCU LVRCR: LVREN (Bit 8)                              */
#define SCU_LVRCR_LVREN_Msk               (0xff00UL)                /*!< SCU LVRCR: LVREN (Bitfield-Mask: 0xff)                */
#define SCU_LVRCR_LVRAON_Pos              (4UL)                     /*!< SCU LVRCR: LVRAON (Bit 4)                             */
#define SCU_LVRCR_LVRAON_Msk              (0x10UL)                  /*!< SCU LVRCR: LVRAON (Bitfield-Mask: 0x01)               */
#define SCU_LVRCR_LVRVS_Pos               (0UL)                     /*!< SCU LVRCR: LVRVS (Bit 0)                              */
#define SCU_LVRCR_LVRVS_Msk               (0xfUL)                   /*!< SCU LVRCR: LVRVS (Bitfield-Mask: 0x0f)                */
/* =========================================================  EOSCR  ========================================================= */
#define SCU_EOSCR_LSEISEL_Pos             (24UL)                    /*!< SCU EOSCR: LSEISEL (Bit 24)                           */
#define SCU_EOSCR_LSEISEL_Msk             (0x3000000UL)             /*!< SCU EOSCR: LSEISEL (Bitfield-Mask: 0x03)              */
#define SCU_EOSCR_LSENFEN_Pos             (16UL)                    /*!< SCU EOSCR: LSENFEN (Bit 16)                           */
#define SCU_EOSCR_LSENFEN_Msk             (0x10000UL)               /*!< SCU EOSCR: LSENFEN (Bitfield-Mask: 0x01)              */
#define SCU_EOSCR_HSEISEL_Pos             (8UL)                     /*!< SCU EOSCR: HSEISEL (Bit 8)                            */
#define SCU_EOSCR_HSEISEL_Msk             (0x300UL)                 /*!< SCU EOSCR: HSEISEL (Bitfield-Mask: 0x03)              */
#define SCU_EOSCR_HSENFEN_Pos             (4UL)                     /*!< SCU EOSCR: HSENFEN (Bit 4)                            */
#define SCU_EOSCR_HSENFEN_Msk             (0x10UL)                  /*!< SCU EOSCR: HSENFEN (Bitfield-Mask: 0x01)              */
#define SCU_EOSCR_HSENFSEL_Pos            (0UL)                     /*!< SCU EOSCR: HSENFSEL (Bit 0)                           */
#define SCU_EOSCR_HSENFSEL_Msk            (0x3UL)                   /*!< SCU EOSCR: HSENFSEL (Bitfield-Mask: 0x03)             */
/* =========================================================  MCCR1  ========================================================= */
#define SCU_MCCR1_WDTCSEL_Pos             (24UL)                    /*!< SCU MCCR1: WDTCSEL (Bit 24)                           */
#define SCU_MCCR1_WDTCSEL_Msk             (0x7000000UL)             /*!< SCU MCCR1: WDTCSEL (Bitfield-Mask: 0x07)              */
#define SCU_MCCR1_WDTCDIV_Pos             (16UL)                    /*!< SCU MCCR1: WDTCDIV (Bit 16)                           */
#define SCU_MCCR1_WDTCDIV_Msk             (0xff0000UL)              /*!< SCU MCCR1: WDTCDIV (Bitfield-Mask: 0xff)              */
#define SCU_MCCR1_STCSEL_Pos              (8UL)                     /*!< SCU MCCR1: STCSEL (Bit 8)                             */
#define SCU_MCCR1_STCSEL_Msk              (0x700UL)                 /*!< SCU MCCR1: STCSEL (Bitfield-Mask: 0x07)               */
#define SCU_MCCR1_STCDIV_Pos              (0UL)                     /*!< SCU MCCR1: STCDIV (Bit 0)                             */
#define SCU_MCCR1_STCDIV_Msk              (0xffUL)                  /*!< SCU MCCR1: STCDIV (Bitfield-Mask: 0xff)               */
/* =========================================================  MCCR2  ========================================================= */
#define SCU_MCCR2_MPWM1CSEL_Pos           (24UL)                    /*!< SCU MCCR2: MPWM1CSEL (Bit 24)                         */
#define SCU_MCCR2_MPWM1CSEL_Msk           (0x7000000UL)             /*!< SCU MCCR2: MPWM1CSEL (Bitfield-Mask: 0x07)            */
#define SCU_MCCR2_MPWM1CDIV_Pos           (16UL)                    /*!< SCU MCCR2: MPWM1CDIV (Bit 16)                         */
#define SCU_MCCR2_MPWM1CDIV_Msk           (0xff0000UL)              /*!< SCU MCCR2: MPWM1CDIV (Bitfield-Mask: 0xff)            */
#define SCU_MCCR2_MPWM0CSEL_Pos           (8UL)                     /*!< SCU MCCR2: MPWM0CSEL (Bit 8)                          */
#define SCU_MCCR2_MPWM0CSEL_Msk           (0x700UL)                 /*!< SCU MCCR2: MPWM0CSEL (Bitfield-Mask: 0x07)            */
#define SCU_MCCR2_MPWM0CDIV_Pos           (0UL)                     /*!< SCU MCCR2: MPWM0CDIV (Bit 0)                          */
#define SCU_MCCR2_MPWM0CDIV_Msk           (0xffUL)                  /*!< SCU MCCR2: MPWM0CDIV (Bitfield-Mask: 0xff)            */
/* =========================================================  MCCR3  ========================================================= */
#define SCU_MCCR3_TIMER59CSEL_Pos         (24UL)                    /*!< SCU MCCR3: TIMER59CSEL (Bit 24)                       */
#define SCU_MCCR3_TIMER59CSEL_Msk         (0x7000000UL)             /*!< SCU MCCR3: TIMER59CSEL (Bitfield-Mask: 0x07)          */
#define SCU_MCCR3_TIMER59CDIV_Pos         (16UL)                    /*!< SCU MCCR3: TIMER59CDIV (Bit 16)                       */
#define SCU_MCCR3_TIMER59CDIV_Msk         (0xff0000UL)              /*!< SCU MCCR3: TIMER59CDIV (Bitfield-Mask: 0xff)          */
#define SCU_MCCR3_TIMER04CSEL_Pos         (8UL)                     /*!< SCU MCCR3: TIMER04CSEL (Bit 8)                        */
#define SCU_MCCR3_TIMER04CSEL_Msk         (0x700UL)                 /*!< SCU MCCR3: TIMER04CSEL (Bitfield-Mask: 0x07)          */
#define SCU_MCCR3_TIMER04CDIV_Pos         (0UL)                     /*!< SCU MCCR3: TIMER04CDIV (Bit 0)                        */
#define SCU_MCCR3_TIMER04CDIV_Msk         (0xffUL)                  /*!< SCU MCCR3: TIMER04CDIV (Bitfield-Mask: 0xff)          */
/* =========================================================  MCCR4  ========================================================= */
#define SCU_MCCR4_PGADCSEL_Pos            (24UL)                    /*!< SCU MCCR4: PGADCSEL (Bit 24)                          */
#define SCU_MCCR4_PGADCSEL_Msk            (0x7000000UL)             /*!< SCU MCCR4: PGADCSEL (Bitfield-Mask: 0x07)             */
#define SCU_MCCR4_PGADCDIV_Pos            (16UL)                    /*!< SCU MCCR4: PGADCDIV (Bit 16)                          */
#define SCU_MCCR4_PGADCDIV_Msk            (0xff0000UL)              /*!< SCU MCCR4: PGADCDIV (Bitfield-Mask: 0xff)             */
/* =========================================================  MCCR5  ========================================================= */
#define SCU_MCCR5_PGCDCSEL_Pos            (24UL)                    /*!< SCU MCCR5: PGCDCSEL (Bit 24)                          */
#define SCU_MCCR5_PGCDCSEL_Msk            (0x7000000UL)             /*!< SCU MCCR5: PGCDCSEL (Bitfield-Mask: 0x07)             */
#define SCU_MCCR5_PGCDCDIV_Pos            (16UL)                    /*!< SCU MCCR5: PGCDCDIV (Bit 16)                          */
#define SCU_MCCR5_PGCDCDIV_Msk            (0xff0000UL)              /*!< SCU MCCR5: PGCDCDIV (Bitfield-Mask: 0xff)             */
#define SCU_MCCR5_PGBDCSEL_Pos            (8UL)                     /*!< SCU MCCR5: PGBDCSEL (Bit 8)                           */
#define SCU_MCCR5_PGBDCSEL_Msk            (0x700UL)                 /*!< SCU MCCR5: PGBDCSEL (Bitfield-Mask: 0x07)             */
#define SCU_MCCR5_PGBDCDIV_Pos            (0UL)                     /*!< SCU MCCR5: PGBDCDIV (Bit 0)                           */
#define SCU_MCCR5_PGBDCDIV_Msk            (0xffUL)                  /*!< SCU MCCR5: PGBDCDIV (Bitfield-Mask: 0xff)             */
/* =========================================================  MCCR6  ========================================================= */
#define SCU_MCCR6_FRT1CSEL_Pos            (24UL)                    /*!< SCU MCCR6: FRT1CSEL (Bit 24)                          */
#define SCU_MCCR6_FRT1CSEL_Msk            (0x7000000UL)             /*!< SCU MCCR6: FRT1CSEL (Bitfield-Mask: 0x07)             */
#define SCU_MCCR6_FRT1CDIV_Pos            (16UL)                    /*!< SCU MCCR6: FRT1CDIV (Bit 16)                          */
#define SCU_MCCR6_FRT1CDIV_Msk            (0xff0000UL)              /*!< SCU MCCR6: FRT1CDIV (Bitfield-Mask: 0xff)             */
#define SCU_MCCR6_FRT0CSEL_Pos            (8UL)                     /*!< SCU MCCR6: FRT0CSEL (Bit 8)                           */
#define SCU_MCCR6_FRT0CSEL_Msk            (0x700UL)                 /*!< SCU MCCR6: FRT0CSEL (Bitfield-Mask: 0x07)             */
#define SCU_MCCR6_FRT0CDIV_Pos            (0UL)                     /*!< SCU MCCR6: FRT0CDIV (Bit 0)                           */
#define SCU_MCCR6_FRT0CDIV_Msk            (0xffUL)                  /*!< SCU MCCR6: FRT0CDIV (Bitfield-Mask: 0xff)             */
/* =========================================================  MCCR7  ========================================================= */
#define SCU_MCCR7_UARTCSEL_Pos            (24UL)                    /*!< SCU MCCR7: UARTCSEL (Bit 24)                          */
#define SCU_MCCR7_UARTCSEL_Msk            (0x7000000UL)             /*!< SCU MCCR7: UARTCSEL (Bitfield-Mask: 0x07)             */
#define SCU_MCCR7_UARTCDIV_Pos            (16UL)                    /*!< SCU MCCR7: UARTCDIV (Bit 16)                          */
#define SCU_MCCR7_UARTCDIV_Msk            (0xff0000UL)              /*!< SCU MCCR7: UARTCDIV (Bitfield-Mask: 0xff)             */
#define SCU_MCCR7_CANCSEL_Pos             (8UL)                     /*!< SCU MCCR7: CANCSEL (Bit 8)                            */
#define SCU_MCCR7_CANCSEL_Msk             (0x700UL)                 /*!< SCU MCCR7: CANCSEL (Bitfield-Mask: 0x07)              */
#define SCU_MCCR7_CANCDIV_Pos             (0UL)                     /*!< SCU MCCR7: CANCDIV (Bit 0)                            */
#define SCU_MCCR7_CANCDIV_Msk             (0xffUL)                  /*!< SCU MCCR7: CANCDIV (Bitfield-Mask: 0xff)              */
/* ========================================================  SYSTEN  ========================================================= */
#define SCU_SYSTEN_ENS_Pos                (8UL)                     /*!< SCU SYSTEN: ENS (Bit 8)                               */
#define SCU_SYSTEN_ENS_Msk                (0x100UL)                 /*!< SCU SYSTEN: ENS (Bitfield-Mask: 0x01)                 */
#define SCU_SYSTEN_SYSTEN_Pos             (0UL)                     /*!< SCU SYSTEN: SYSTEN (Bit 0)                            */
#define SCU_SYSTEN_SYSTEN_Msk             (0xffUL)                  /*!< SCU SYSTEN: SYSTEN (Bitfield-Mask: 0xff)              */


/* =========================================================================================================================== */
/* ================                                            PCU                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  MR1  ========================================================== */
#define PCU_MR1_P7MUX_Pos                 (28UL)                    /*!< PCU MR1: P7MUX (Bit 28)                               */
#define PCU_MR1_P7MUX_Msk                 (0x70000000UL)            /*!< PCU MR1: P7MUX (Bitfield-Mask: 0x07)                  */
#define PCU_MR1_P6MUX_Pos                 (24UL)                    /*!< PCU MR1: P6MUX (Bit 24)                               */
#define PCU_MR1_P6MUX_Msk                 (0x7000000UL)             /*!< PCU MR1: P6MUX (Bitfield-Mask: 0x07)                  */
#define PCU_MR1_P5MUX_Pos                 (20UL)                    /*!< PCU MR1: P5MUX (Bit 20)                               */
#define PCU_MR1_P5MUX_Msk                 (0x700000UL)              /*!< PCU MR1: P5MUX (Bitfield-Mask: 0x07)                  */
#define PCU_MR1_P4MUX_Pos                 (16UL)                    /*!< PCU MR1: P4MUX (Bit 16)                               */
#define PCU_MR1_P4MUX_Msk                 (0x70000UL)               /*!< PCU MR1: P4MUX (Bitfield-Mask: 0x07)                  */
#define PCU_MR1_P3MUX_Pos                 (12UL)                    /*!< PCU MR1: P3MUX (Bit 12)                               */
#define PCU_MR1_P3MUX_Msk                 (0x7000UL)                /*!< PCU MR1: P3MUX (Bitfield-Mask: 0x07)                  */
#define PCU_MR1_P2MUX_Pos                 (8UL)                     /*!< PCU MR1: P2MUX (Bit 8)                                */
#define PCU_MR1_P2MUX_Msk                 (0x700UL)                 /*!< PCU MR1: P2MUX (Bitfield-Mask: 0x07)                  */
#define PCU_MR1_P1MUX_Pos                 (4UL)                     /*!< PCU MR1: P1MUX (Bit 4)                                */
#define PCU_MR1_P1MUX_Msk                 (0x70UL)                  /*!< PCU MR1: P1MUX (Bitfield-Mask: 0x07)                  */
#define PCU_MR1_P0MUX_Pos                 (0UL)                     /*!< PCU MR1: P0MUX (Bit 0)                                */
#define PCU_MR1_P0MUX_Msk                 (0x7UL)                   /*!< PCU MR1: P0MUX (Bitfield-Mask: 0x07)                  */
/* ==========================================================  MR2  ========================================================== */
#define PCU_MR2_P15MUX_Pos                (28UL)                    /*!< PCU MR2: P15MUX (Bit 28)                              */
#define PCU_MR2_P15MUX_Msk                (0x70000000UL)            /*!< PCU MR2: P15MUX (Bitfield-Mask: 0x07)                 */
#define PCU_MR2_P14MUX_Pos                (24UL)                    /*!< PCU MR2: P14MUX (Bit 24)                              */
#define PCU_MR2_P14MUX_Msk                (0x7000000UL)             /*!< PCU MR2: P14MUX (Bitfield-Mask: 0x07)                 */
#define PCU_MR2_P13MUX_Pos                (20UL)                    /*!< PCU MR2: P13MUX (Bit 20)                              */
#define PCU_MR2_P13MUX_Msk                (0x700000UL)              /*!< PCU MR2: P13MUX (Bitfield-Mask: 0x07)                 */
#define PCU_MR2_P12MUX_Pos                (16UL)                    /*!< PCU MR2: P12MUX (Bit 16)                              */
#define PCU_MR2_P12MUX_Msk                (0x70000UL)               /*!< PCU MR2: P12MUX (Bitfield-Mask: 0x07)                 */
#define PCU_MR2_P11MUX_Pos                (12UL)                    /*!< PCU MR2: P11MUX (Bit 12)                              */
#define PCU_MR2_P11MUX_Msk                (0x7000UL)                /*!< PCU MR2: P11MUX (Bitfield-Mask: 0x07)                 */
#define PCU_MR2_P10MUX_Pos                (8UL)                     /*!< PCU MR2: P10MUX (Bit 8)                               */
#define PCU_MR2_P10MUX_Msk                (0x700UL)                 /*!< PCU MR2: P10MUX (Bitfield-Mask: 0x07)                 */
#define PCU_MR2_P9MUX_Pos                 (4UL)                     /*!< PCU MR2: P9MUX (Bit 4)                                */
#define PCU_MR2_P9MUX_Msk                 (0x70UL)                  /*!< PCU MR2: P9MUX (Bitfield-Mask: 0x07)                  */
#define PCU_MR2_P8MUX_Pos                 (0UL)                     /*!< PCU MR2: P8MUX (Bit 0)                                */
#define PCU_MR2_P8MUX_Msk                 (0x7UL)                   /*!< PCU MR2: P8MUX (Bitfield-Mask: 0x07)                  */
/* ==========================================================  CR  =========================================================== */
#define PCU_CR_P15_Pos                    (30UL)                    /*!< PCU CR: P15 (Bit 30)                                  */
#define PCU_CR_P15_Msk                    (0xc0000000UL)            /*!< PCU CR: P15 (Bitfield-Mask: 0x03)                     */
#define PCU_CR_P14_Pos                    (28UL)                    /*!< PCU CR: P14 (Bit 28)                                  */
#define PCU_CR_P14_Msk                    (0x30000000UL)            /*!< PCU CR: P14 (Bitfield-Mask: 0x03)                     */
#define PCU_CR_P13_Pos                    (26UL)                    /*!< PCU CR: P13 (Bit 26)                                  */
#define PCU_CR_P13_Msk                    (0xc000000UL)             /*!< PCU CR: P13 (Bitfield-Mask: 0x03)                     */
#define PCU_CR_P12_Pos                    (24UL)                    /*!< PCU CR: P12 (Bit 24)                                  */
#define PCU_CR_P12_Msk                    (0x3000000UL)             /*!< PCU CR: P12 (Bitfield-Mask: 0x03)                     */
#define PCU_CR_P11_Pos                    (22UL)                    /*!< PCU CR: P11 (Bit 22)                                  */
#define PCU_CR_P11_Msk                    (0xc00000UL)              /*!< PCU CR: P11 (Bitfield-Mask: 0x03)                     */
#define PCU_CR_P10_Pos                    (20UL)                    /*!< PCU CR: P10 (Bit 20)                                  */
#define PCU_CR_P10_Msk                    (0x300000UL)              /*!< PCU CR: P10 (Bitfield-Mask: 0x03)                     */
#define PCU_CR_P9_Pos                     (18UL)                    /*!< PCU CR: P9 (Bit 18)                                   */
#define PCU_CR_P9_Msk                     (0xc0000UL)               /*!< PCU CR: P9 (Bitfield-Mask: 0x03)                      */
#define PCU_CR_P8_Pos                     (16UL)                    /*!< PCU CR: P8 (Bit 16)                                   */
#define PCU_CR_P8_Msk                     (0x30000UL)               /*!< PCU CR: P8 (Bitfield-Mask: 0x03)                      */
#define PCU_CR_P7_Pos                     (14UL)                    /*!< PCU CR: P7 (Bit 14)                                   */
#define PCU_CR_P7_Msk                     (0xc000UL)                /*!< PCU CR: P7 (Bitfield-Mask: 0x03)                      */
#define PCU_CR_P6_Pos                     (12UL)                    /*!< PCU CR: P6 (Bit 12)                                   */
#define PCU_CR_P6_Msk                     (0x3000UL)                /*!< PCU CR: P6 (Bitfield-Mask: 0x03)                      */
#define PCU_CR_P5_Pos                     (10UL)                    /*!< PCU CR: P5 (Bit 10)                                   */
#define PCU_CR_P5_Msk                     (0xc00UL)                 /*!< PCU CR: P5 (Bitfield-Mask: 0x03)                      */
#define PCU_CR_P4_Pos                     (8UL)                     /*!< PCU CR: P4 (Bit 8)                                    */
#define PCU_CR_P4_Msk                     (0x300UL)                 /*!< PCU CR: P4 (Bitfield-Mask: 0x03)                      */
#define PCU_CR_P3_Pos                     (6UL)                     /*!< PCU CR: P3 (Bit 6)                                    */
#define PCU_CR_P3_Msk                     (0xc0UL)                  /*!< PCU CR: P3 (Bitfield-Mask: 0x03)                      */
#define PCU_CR_P2_Pos                     (4UL)                     /*!< PCU CR: P2 (Bit 4)                                    */
#define PCU_CR_P2_Msk                     (0x30UL)                  /*!< PCU CR: P2 (Bitfield-Mask: 0x03)                      */
#define PCU_CR_P1_Pos                     (2UL)                     /*!< PCU CR: P1 (Bit 2)                                    */
#define PCU_CR_P1_Msk                     (0xcUL)                   /*!< PCU CR: P1 (Bitfield-Mask: 0x03)                      */
#define PCU_CR_P0_Pos                     (0UL)                     /*!< PCU CR: P0 (Bit 0)                                    */
#define PCU_CR_P0_Msk                     (0x3UL)                   /*!< PCU CR: P0 (Bitfield-Mask: 0x03)                      */
/* =========================================================  PRCR  ========================================================== */
#define PCU_PRCR_PUE15_Pos                (30UL)                    /*!< PCU PRCR: PUE15 (Bit 30)                              */
#define PCU_PRCR_PUE15_Msk                (0xc0000000UL)            /*!< PCU PRCR: PUE15 (Bitfield-Mask: 0x03)                 */
#define PCU_PRCR_PUE14_Pos                (28UL)                    /*!< PCU PRCR: PUE14 (Bit 28)                              */
#define PCU_PRCR_PUE14_Msk                (0x30000000UL)            /*!< PCU PRCR: PUE14 (Bitfield-Mask: 0x03)                 */
#define PCU_PRCR_PUE13_Pos                (26UL)                    /*!< PCU PRCR: PUE13 (Bit 26)                              */
#define PCU_PRCR_PUE13_Msk                (0xc000000UL)             /*!< PCU PRCR: PUE13 (Bitfield-Mask: 0x03)                 */
#define PCU_PRCR_PUE12_Pos                (24UL)                    /*!< PCU PRCR: PUE12 (Bit 24)                              */
#define PCU_PRCR_PUE12_Msk                (0x3000000UL)             /*!< PCU PRCR: PUE12 (Bitfield-Mask: 0x03)                 */
#define PCU_PRCR_PUE11_Pos                (22UL)                    /*!< PCU PRCR: PUE11 (Bit 22)                              */
#define PCU_PRCR_PUE11_Msk                (0xc00000UL)              /*!< PCU PRCR: PUE11 (Bitfield-Mask: 0x03)                 */
#define PCU_PRCR_PUE10_Pos                (20UL)                    /*!< PCU PRCR: PUE10 (Bit 20)                              */
#define PCU_PRCR_PUE10_Msk                (0x300000UL)              /*!< PCU PRCR: PUE10 (Bitfield-Mask: 0x03)                 */
#define PCU_PRCR_PUE9_Pos                 (18UL)                    /*!< PCU PRCR: PUE9 (Bit 18)                               */
#define PCU_PRCR_PUE9_Msk                 (0xc0000UL)               /*!< PCU PRCR: PUE9 (Bitfield-Mask: 0x03)                  */
#define PCU_PRCR_PUE8_Pos                 (16UL)                    /*!< PCU PRCR: PUE8 (Bit 16)                               */
#define PCU_PRCR_PUE8_Msk                 (0x30000UL)               /*!< PCU PRCR: PUE8 (Bitfield-Mask: 0x03)                  */
#define PCU_PRCR_PUE7_Pos                 (14UL)                    /*!< PCU PRCR: PUE7 (Bit 14)                               */
#define PCU_PRCR_PUE7_Msk                 (0xc000UL)                /*!< PCU PRCR: PUE7 (Bitfield-Mask: 0x03)                  */
#define PCU_PRCR_PUE6_Pos                 (12UL)                    /*!< PCU PRCR: PUE6 (Bit 12)                               */
#define PCU_PRCR_PUE6_Msk                 (0x3000UL)                /*!< PCU PRCR: PUE6 (Bitfield-Mask: 0x03)                  */
#define PCU_PRCR_PUE5_Pos                 (10UL)                    /*!< PCU PRCR: PUE5 (Bit 10)                               */
#define PCU_PRCR_PUE5_Msk                 (0xc00UL)                 /*!< PCU PRCR: PUE5 (Bitfield-Mask: 0x03)                  */
#define PCU_PRCR_PUE4_Pos                 (8UL)                     /*!< PCU PRCR: PUE4 (Bit 8)                                */
#define PCU_PRCR_PUE4_Msk                 (0x300UL)                 /*!< PCU PRCR: PUE4 (Bitfield-Mask: 0x03)                  */
#define PCU_PRCR_PUE3_Pos                 (6UL)                     /*!< PCU PRCR: PUE3 (Bit 6)                                */
#define PCU_PRCR_PUE3_Msk                 (0xc0UL)                  /*!< PCU PRCR: PUE3 (Bitfield-Mask: 0x03)                  */
#define PCU_PRCR_PUE2_Pos                 (4UL)                     /*!< PCU PRCR: PUE2 (Bit 4)                                */
#define PCU_PRCR_PUE2_Msk                 (0x30UL)                  /*!< PCU PRCR: PUE2 (Bitfield-Mask: 0x03)                  */
#define PCU_PRCR_PUE1_Pos                 (2UL)                     /*!< PCU PRCR: PUE1 (Bit 2)                                */
#define PCU_PRCR_PUE1_Msk                 (0xcUL)                   /*!< PCU PRCR: PUE1 (Bitfield-Mask: 0x03)                  */
#define PCU_PRCR_PUE0_Pos                 (0UL)                     /*!< PCU PRCR: PUE0 (Bit 0)                                */
#define PCU_PRCR_PUE0_Msk                 (0x3UL)                   /*!< PCU PRCR: PUE0 (Bitfield-Mask: 0x03)                  */
/* ==========================================================  DER  ========================================================== */
#define PCU_DER_PDE15_Pos                 (15UL)                    /*!< PCU DER: PDE15 (Bit 15)                               */
#define PCU_DER_PDE15_Msk                 (0x8000UL)                /*!< PCU DER: PDE15 (Bitfield-Mask: 0x01)                  */
#define PCU_DER_PDE14_Pos                 (14UL)                    /*!< PCU DER: PDE14 (Bit 14)                               */
#define PCU_DER_PDE14_Msk                 (0x4000UL)                /*!< PCU DER: PDE14 (Bitfield-Mask: 0x01)                  */
#define PCU_DER_PDE13_Pos                 (13UL)                    /*!< PCU DER: PDE13 (Bit 13)                               */
#define PCU_DER_PDE13_Msk                 (0x2000UL)                /*!< PCU DER: PDE13 (Bitfield-Mask: 0x01)                  */
#define PCU_DER_PDE12_Pos                 (12UL)                    /*!< PCU DER: PDE12 (Bit 12)                               */
#define PCU_DER_PDE12_Msk                 (0x1000UL)                /*!< PCU DER: PDE12 (Bitfield-Mask: 0x01)                  */
#define PCU_DER_PDE11_Pos                 (11UL)                    /*!< PCU DER: PDE11 (Bit 11)                               */
#define PCU_DER_PDE11_Msk                 (0x800UL)                 /*!< PCU DER: PDE11 (Bitfield-Mask: 0x01)                  */
#define PCU_DER_PDE10_Pos                 (10UL)                    /*!< PCU DER: PDE10 (Bit 10)                               */
#define PCU_DER_PDE10_Msk                 (0x400UL)                 /*!< PCU DER: PDE10 (Bitfield-Mask: 0x01)                  */
#define PCU_DER_PDE9_Pos                  (9UL)                     /*!< PCU DER: PDE9 (Bit 9)                                 */
#define PCU_DER_PDE9_Msk                  (0x200UL)                 /*!< PCU DER: PDE9 (Bitfield-Mask: 0x01)                   */
#define PCU_DER_PDE8_Pos                  (8UL)                     /*!< PCU DER: PDE8 (Bit 8)                                 */
#define PCU_DER_PDE8_Msk                  (0x100UL)                 /*!< PCU DER: PDE8 (Bitfield-Mask: 0x01)                   */
#define PCU_DER_PDE7_Pos                  (7UL)                     /*!< PCU DER: PDE7 (Bit 7)                                 */
#define PCU_DER_PDE7_Msk                  (0x80UL)                  /*!< PCU DER: PDE7 (Bitfield-Mask: 0x01)                   */
#define PCU_DER_PDE6_Pos                  (6UL)                     /*!< PCU DER: PDE6 (Bit 6)                                 */
#define PCU_DER_PDE6_Msk                  (0x40UL)                  /*!< PCU DER: PDE6 (Bitfield-Mask: 0x01)                   */
#define PCU_DER_PDE5_Pos                  (5UL)                     /*!< PCU DER: PDE5 (Bit 5)                                 */
#define PCU_DER_PDE5_Msk                  (0x20UL)                  /*!< PCU DER: PDE5 (Bitfield-Mask: 0x01)                   */
#define PCU_DER_PDE4_Pos                  (4UL)                     /*!< PCU DER: PDE4 (Bit 4)                                 */
#define PCU_DER_PDE4_Msk                  (0x10UL)                  /*!< PCU DER: PDE4 (Bitfield-Mask: 0x01)                   */
#define PCU_DER_PDE3_Pos                  (3UL)                     /*!< PCU DER: PDE3 (Bit 3)                                 */
#define PCU_DER_PDE3_Msk                  (0x8UL)                   /*!< PCU DER: PDE3 (Bitfield-Mask: 0x01)                   */
#define PCU_DER_PDE2_Pos                  (2UL)                     /*!< PCU DER: PDE2 (Bit 2)                                 */
#define PCU_DER_PDE2_Msk                  (0x4UL)                   /*!< PCU DER: PDE2 (Bitfield-Mask: 0x01)                   */
#define PCU_DER_PDE1_Pos                  (1UL)                     /*!< PCU DER: PDE1 (Bit 1)                                 */
#define PCU_DER_PDE1_Msk                  (0x2UL)                   /*!< PCU DER: PDE1 (Bitfield-Mask: 0x01)                   */
#define PCU_DER_PDE0_Pos                  (0UL)                     /*!< PCU DER: PDE0 (Bit 0)                                 */
#define PCU_DER_PDE0_Msk                  (0x1UL)                   /*!< PCU DER: PDE0 (Bitfield-Mask: 0x01)                   */
/* ==========================================================  STR  ========================================================== */
#define PCU_STR_PST15_Pos                 (15UL)                    /*!< PCU STR: PST15 (Bit 15)                               */
#define PCU_STR_PST15_Msk                 (0x8000UL)                /*!< PCU STR: PST15 (Bitfield-Mask: 0x01)                  */
#define PCU_STR_PST14_Pos                 (14UL)                    /*!< PCU STR: PST14 (Bit 14)                               */
#define PCU_STR_PST14_Msk                 (0x4000UL)                /*!< PCU STR: PST14 (Bitfield-Mask: 0x01)                  */
#define PCU_STR_PST13_Pos                 (13UL)                    /*!< PCU STR: PST13 (Bit 13)                               */
#define PCU_STR_PST13_Msk                 (0x2000UL)                /*!< PCU STR: PST13 (Bitfield-Mask: 0x01)                  */
#define PCU_STR_PST12_Pos                 (12UL)                    /*!< PCU STR: PST12 (Bit 12)                               */
#define PCU_STR_PST12_Msk                 (0x1000UL)                /*!< PCU STR: PST12 (Bitfield-Mask: 0x01)                  */
#define PCU_STR_PST11_Pos                 (11UL)                    /*!< PCU STR: PST11 (Bit 11)                               */
#define PCU_STR_PST11_Msk                 (0x800UL)                 /*!< PCU STR: PST11 (Bitfield-Mask: 0x01)                  */
#define PCU_STR_PST10_Pos                 (10UL)                    /*!< PCU STR: PST10 (Bit 10)                               */
#define PCU_STR_PST10_Msk                 (0x400UL)                 /*!< PCU STR: PST10 (Bitfield-Mask: 0x01)                  */
#define PCU_STR_PST9_Pos                  (9UL)                     /*!< PCU STR: PST9 (Bit 9)                                 */
#define PCU_STR_PST9_Msk                  (0x200UL)                 /*!< PCU STR: PST9 (Bitfield-Mask: 0x01)                   */
#define PCU_STR_PST8_Pos                  (8UL)                     /*!< PCU STR: PST8 (Bit 8)                                 */
#define PCU_STR_PST8_Msk                  (0x100UL)                 /*!< PCU STR: PST8 (Bitfield-Mask: 0x01)                   */
#define PCU_STR_PST7_Pos                  (7UL)                     /*!< PCU STR: PST7 (Bit 7)                                 */
#define PCU_STR_PST7_Msk                  (0x80UL)                  /*!< PCU STR: PST7 (Bitfield-Mask: 0x01)                   */
#define PCU_STR_PST6_Pos                  (6UL)                     /*!< PCU STR: PST6 (Bit 6)                                 */
#define PCU_STR_PST6_Msk                  (0x40UL)                  /*!< PCU STR: PST6 (Bitfield-Mask: 0x01)                   */
#define PCU_STR_PST5_Pos                  (5UL)                     /*!< PCU STR: PST5 (Bit 5)                                 */
#define PCU_STR_PST5_Msk                  (0x20UL)                  /*!< PCU STR: PST5 (Bitfield-Mask: 0x01)                   */
#define PCU_STR_PST4_Pos                  (4UL)                     /*!< PCU STR: PST4 (Bit 4)                                 */
#define PCU_STR_PST4_Msk                  (0x10UL)                  /*!< PCU STR: PST4 (Bitfield-Mask: 0x01)                   */
#define PCU_STR_PST3_Pos                  (3UL)                     /*!< PCU STR: PST3 (Bit 3)                                 */
#define PCU_STR_PST3_Msk                  (0x8UL)                   /*!< PCU STR: PST3 (Bitfield-Mask: 0x01)                   */
#define PCU_STR_PST2_Pos                  (2UL)                     /*!< PCU STR: PST2 (Bit 2)                                 */
#define PCU_STR_PST2_Msk                  (0x4UL)                   /*!< PCU STR: PST2 (Bitfield-Mask: 0x01)                   */
#define PCU_STR_PST1_Pos                  (1UL)                     /*!< PCU STR: PST1 (Bit 1)                                 */
#define PCU_STR_PST1_Msk                  (0x2UL)                   /*!< PCU STR: PST1 (Bitfield-Mask: 0x01)                   */
#define PCU_STR_PST0_Pos                  (0UL)                     /*!< PCU STR: PST0 (Bit 0)                                 */
#define PCU_STR_PST0_Msk                  (0x1UL)                   /*!< PCU STR: PST0 (Bitfield-Mask: 0x01)                   */
/* ==========================================================  IER  ========================================================== */
#define PCU_IER_PIE15_Pos                 (30UL)                    /*!< PCU IER: PIE15 (Bit 30)                               */
#define PCU_IER_PIE15_Msk                 (0xc0000000UL)            /*!< PCU IER: PIE15 (Bitfield-Mask: 0x03)                  */
#define PCU_IER_PIE14_Pos                 (28UL)                    /*!< PCU IER: PIE14 (Bit 28)                               */
#define PCU_IER_PIE14_Msk                 (0x30000000UL)            /*!< PCU IER: PIE14 (Bitfield-Mask: 0x03)                  */
#define PCU_IER_PIE13_Pos                 (26UL)                    /*!< PCU IER: PIE13 (Bit 26)                               */
#define PCU_IER_PIE13_Msk                 (0xc000000UL)             /*!< PCU IER: PIE13 (Bitfield-Mask: 0x03)                  */
#define PCU_IER_PIE12_Pos                 (24UL)                    /*!< PCU IER: PIE12 (Bit 24)                               */
#define PCU_IER_PIE12_Msk                 (0x3000000UL)             /*!< PCU IER: PIE12 (Bitfield-Mask: 0x03)                  */
#define PCU_IER_PIE11_Pos                 (22UL)                    /*!< PCU IER: PIE11 (Bit 22)                               */
#define PCU_IER_PIE11_Msk                 (0xc00000UL)              /*!< PCU IER: PIE11 (Bitfield-Mask: 0x03)                  */
#define PCU_IER_PIE10_Pos                 (20UL)                    /*!< PCU IER: PIE10 (Bit 20)                               */
#define PCU_IER_PIE10_Msk                 (0x300000UL)              /*!< PCU IER: PIE10 (Bitfield-Mask: 0x03)                  */
#define PCU_IER_PIE9_Pos                  (18UL)                    /*!< PCU IER: PIE9 (Bit 18)                                */
#define PCU_IER_PIE9_Msk                  (0xc0000UL)               /*!< PCU IER: PIE9 (Bitfield-Mask: 0x03)                   */
#define PCU_IER_PIE8_Pos                  (16UL)                    /*!< PCU IER: PIE8 (Bit 16)                                */
#define PCU_IER_PIE8_Msk                  (0x30000UL)               /*!< PCU IER: PIE8 (Bitfield-Mask: 0x03)                   */
#define PCU_IER_PIE7_Pos                  (14UL)                    /*!< PCU IER: PIE7 (Bit 14)                                */
#define PCU_IER_PIE7_Msk                  (0xc000UL)                /*!< PCU IER: PIE7 (Bitfield-Mask: 0x03)                   */
#define PCU_IER_PIE6_Pos                  (12UL)                    /*!< PCU IER: PIE6 (Bit 12)                                */
#define PCU_IER_PIE6_Msk                  (0x3000UL)                /*!< PCU IER: PIE6 (Bitfield-Mask: 0x03)                   */
#define PCU_IER_PIE5_Pos                  (10UL)                    /*!< PCU IER: PIE5 (Bit 10)                                */
#define PCU_IER_PIE5_Msk                  (0xc00UL)                 /*!< PCU IER: PIE5 (Bitfield-Mask: 0x03)                   */
#define PCU_IER_PIE4_Pos                  (8UL)                     /*!< PCU IER: PIE4 (Bit 8)                                 */
#define PCU_IER_PIE4_Msk                  (0x300UL)                 /*!< PCU IER: PIE4 (Bitfield-Mask: 0x03)                   */
#define PCU_IER_PIE3_Pos                  (6UL)                     /*!< PCU IER: PIE3 (Bit 6)                                 */
#define PCU_IER_PIE3_Msk                  (0xc0UL)                  /*!< PCU IER: PIE3 (Bitfield-Mask: 0x03)                   */
#define PCU_IER_PIE2_Pos                  (4UL)                     /*!< PCU IER: PIE2 (Bit 4)                                 */
#define PCU_IER_PIE2_Msk                  (0x30UL)                  /*!< PCU IER: PIE2 (Bitfield-Mask: 0x03)                   */
#define PCU_IER_PIE1_Pos                  (2UL)                     /*!< PCU IER: PIE1 (Bit 2)                                 */
#define PCU_IER_PIE1_Msk                  (0xcUL)                   /*!< PCU IER: PIE1 (Bitfield-Mask: 0x03)                   */
#define PCU_IER_PIE0_Pos                  (0UL)                     /*!< PCU IER: PIE0 (Bit 0)                                 */
#define PCU_IER_PIE0_Msk                  (0x3UL)                   /*!< PCU IER: PIE0 (Bitfield-Mask: 0x03)                   */
/* ==========================================================  ISR  ========================================================== */
#define PCU_ISR_PIS15_Pos                 (30UL)                    /*!< PCU ISR: PIS15 (Bit 30)                               */
#define PCU_ISR_PIS15_Msk                 (0xc0000000UL)            /*!< PCU ISR: PIS15 (Bitfield-Mask: 0x03)                  */
#define PCU_ISR_PIS14_Pos                 (28UL)                    /*!< PCU ISR: PIS14 (Bit 28)                               */
#define PCU_ISR_PIS14_Msk                 (0x30000000UL)            /*!< PCU ISR: PIS14 (Bitfield-Mask: 0x03)                  */
#define PCU_ISR_PIS13_Pos                 (26UL)                    /*!< PCU ISR: PIS13 (Bit 26)                               */
#define PCU_ISR_PIS13_Msk                 (0xc000000UL)             /*!< PCU ISR: PIS13 (Bitfield-Mask: 0x03)                  */
#define PCU_ISR_PIS12_Pos                 (24UL)                    /*!< PCU ISR: PIS12 (Bit 24)                               */
#define PCU_ISR_PIS12_Msk                 (0x3000000UL)             /*!< PCU ISR: PIS12 (Bitfield-Mask: 0x03)                  */
#define PCU_ISR_PIS11_Pos                 (22UL)                    /*!< PCU ISR: PIS11 (Bit 22)                               */
#define PCU_ISR_PIS11_Msk                 (0xc00000UL)              /*!< PCU ISR: PIS11 (Bitfield-Mask: 0x03)                  */
#define PCU_ISR_PIS10_Pos                 (20UL)                    /*!< PCU ISR: PIS10 (Bit 20)                               */
#define PCU_ISR_PIS10_Msk                 (0x300000UL)              /*!< PCU ISR: PIS10 (Bitfield-Mask: 0x03)                  */
#define PCU_ISR_PIS9_Pos                  (18UL)                    /*!< PCU ISR: PIS9 (Bit 18)                                */
#define PCU_ISR_PIS9_Msk                  (0xc0000UL)               /*!< PCU ISR: PIS9 (Bitfield-Mask: 0x03)                   */
#define PCU_ISR_PIS8_Pos                  (16UL)                    /*!< PCU ISR: PIS8 (Bit 16)                                */
#define PCU_ISR_PIS8_Msk                  (0x30000UL)               /*!< PCU ISR: PIS8 (Bitfield-Mask: 0x03)                   */
#define PCU_ISR_PIS7_Pos                  (14UL)                    /*!< PCU ISR: PIS7 (Bit 14)                                */
#define PCU_ISR_PIS7_Msk                  (0xc000UL)                /*!< PCU ISR: PIS7 (Bitfield-Mask: 0x03)                   */
#define PCU_ISR_PIS6_Pos                  (12UL)                    /*!< PCU ISR: PIS6 (Bit 12)                                */
#define PCU_ISR_PIS6_Msk                  (0x3000UL)                /*!< PCU ISR: PIS6 (Bitfield-Mask: 0x03)                   */
#define PCU_ISR_PIS5_Pos                  (10UL)                    /*!< PCU ISR: PIS5 (Bit 10)                                */
#define PCU_ISR_PIS5_Msk                  (0xc00UL)                 /*!< PCU ISR: PIS5 (Bitfield-Mask: 0x03)                   */
#define PCU_ISR_PIS4_Pos                  (8UL)                     /*!< PCU ISR: PIS4 (Bit 8)                                 */
#define PCU_ISR_PIS4_Msk                  (0x300UL)                 /*!< PCU ISR: PIS4 (Bitfield-Mask: 0x03)                   */
#define PCU_ISR_PIS3_Pos                  (6UL)                     /*!< PCU ISR: PIS3 (Bit 6)                                 */
#define PCU_ISR_PIS3_Msk                  (0xc0UL)                  /*!< PCU ISR: PIS3 (Bitfield-Mask: 0x03)                   */
#define PCU_ISR_PIS2_Pos                  (4UL)                     /*!< PCU ISR: PIS2 (Bit 4)                                 */
#define PCU_ISR_PIS2_Msk                  (0x30UL)                  /*!< PCU ISR: PIS2 (Bitfield-Mask: 0x03)                   */
#define PCU_ISR_PIS1_Pos                  (2UL)                     /*!< PCU ISR: PIS1 (Bit 2)                                 */
#define PCU_ISR_PIS1_Msk                  (0xcUL)                   /*!< PCU ISR: PIS1 (Bitfield-Mask: 0x03)                   */
#define PCU_ISR_PIS0_Pos                  (0UL)                     /*!< PCU ISR: PIS0 (Bit 0)                                 */
#define PCU_ISR_PIS0_Msk                  (0x3UL)                   /*!< PCU ISR: PIS0 (Bitfield-Mask: 0x03)                   */
/* ==========================================================  ICR  ========================================================== */
#define PCU_ICR_PIC15_Pos                 (30UL)                    /*!< PCU ICR: PIC15 (Bit 30)                               */
#define PCU_ICR_PIC15_Msk                 (0xc0000000UL)            /*!< PCU ICR: PIC15 (Bitfield-Mask: 0x03)                  */
#define PCU_ICR_PIC14_Pos                 (28UL)                    /*!< PCU ICR: PIC14 (Bit 28)                               */
#define PCU_ICR_PIC14_Msk                 (0x30000000UL)            /*!< PCU ICR: PIC14 (Bitfield-Mask: 0x03)                  */
#define PCU_ICR_PIC13_Pos                 (26UL)                    /*!< PCU ICR: PIC13 (Bit 26)                               */
#define PCU_ICR_PIC13_Msk                 (0xc000000UL)             /*!< PCU ICR: PIC13 (Bitfield-Mask: 0x03)                  */
#define PCU_ICR_PIC12_Pos                 (24UL)                    /*!< PCU ICR: PIC12 (Bit 24)                               */
#define PCU_ICR_PIC12_Msk                 (0x3000000UL)             /*!< PCU ICR: PIC12 (Bitfield-Mask: 0x03)                  */
#define PCU_ICR_PIC11_Pos                 (22UL)                    /*!< PCU ICR: PIC11 (Bit 22)                               */
#define PCU_ICR_PIC11_Msk                 (0xc00000UL)              /*!< PCU ICR: PIC11 (Bitfield-Mask: 0x03)                  */
#define PCU_ICR_PIC10_Pos                 (20UL)                    /*!< PCU ICR: PIC10 (Bit 20)                               */
#define PCU_ICR_PIC10_Msk                 (0x300000UL)              /*!< PCU ICR: PIC10 (Bitfield-Mask: 0x03)                  */
#define PCU_ICR_PIC9_Pos                  (18UL)                    /*!< PCU ICR: PIC9 (Bit 18)                                */
#define PCU_ICR_PIC9_Msk                  (0xc0000UL)               /*!< PCU ICR: PIC9 (Bitfield-Mask: 0x03)                   */
#define PCU_ICR_PIC8_Pos                  (16UL)                    /*!< PCU ICR: PIC8 (Bit 16)                                */
#define PCU_ICR_PIC8_Msk                  (0x30000UL)               /*!< PCU ICR: PIC8 (Bitfield-Mask: 0x03)                   */
#define PCU_ICR_PIC7_Pos                  (14UL)                    /*!< PCU ICR: PIC7 (Bit 14)                                */
#define PCU_ICR_PIC7_Msk                  (0xc000UL)                /*!< PCU ICR: PIC7 (Bitfield-Mask: 0x03)                   */
#define PCU_ICR_PIC6_Pos                  (12UL)                    /*!< PCU ICR: PIC6 (Bit 12)                                */
#define PCU_ICR_PIC6_Msk                  (0x3000UL)                /*!< PCU ICR: PIC6 (Bitfield-Mask: 0x03)                   */
#define PCU_ICR_PIC5_Pos                  (10UL)                    /*!< PCU ICR: PIC5 (Bit 10)                                */
#define PCU_ICR_PIC5_Msk                  (0xc00UL)                 /*!< PCU ICR: PIC5 (Bitfield-Mask: 0x03)                   */
#define PCU_ICR_PIC4_Pos                  (8UL)                     /*!< PCU ICR: PIC4 (Bit 8)                                 */
#define PCU_ICR_PIC4_Msk                  (0x300UL)                 /*!< PCU ICR: PIC4 (Bitfield-Mask: 0x03)                   */
#define PCU_ICR_PIC3_Pos                  (6UL)                     /*!< PCU ICR: PIC3 (Bit 6)                                 */
#define PCU_ICR_PIC3_Msk                  (0xc0UL)                  /*!< PCU ICR: PIC3 (Bitfield-Mask: 0x03)                   */
#define PCU_ICR_PIC2_Pos                  (4UL)                     /*!< PCU ICR: PIC2 (Bit 4)                                 */
#define PCU_ICR_PIC2_Msk                  (0x30UL)                  /*!< PCU ICR: PIC2 (Bitfield-Mask: 0x03)                   */
#define PCU_ICR_PIC1_Pos                  (2UL)                     /*!< PCU ICR: PIC1 (Bit 2)                                 */
#define PCU_ICR_PIC1_Msk                  (0xcUL)                   /*!< PCU ICR: PIC1 (Bitfield-Mask: 0x03)                   */
#define PCU_ICR_PIC0_Pos                  (0UL)                     /*!< PCU ICR: PIC0 (Bit 0)                                 */
#define PCU_ICR_PIC0_Msk                  (0x3UL)                   /*!< PCU ICR: PIC0 (Bitfield-Mask: 0x03)                   */
/* ==========================================================  ODR  ========================================================== */
#define PCU_ODR_POD_Pos                   (0UL)                     /*!< PCU ODR: POD (Bit 0)                                  */
#define PCU_ODR_POD_Msk                   (0xffffUL)                /*!< PCU ODR: POD (Bitfield-Mask: 0xffff)                  */
/* ==========================================================  IDR  ========================================================== */
#define PCU_IDR_PID_Pos                   (0UL)                     /*!< PCU IDR: PID (Bit 0)                                  */
#define PCU_IDR_PID_Msk                   (0xffffUL)                /*!< PCU IDR: PID (Bitfield-Mask: 0xffff)                  */
/* ==========================================================  PSR  ========================================================== */
#define PCU_PSR_BSD15_Pos                 (15UL)                    /*!< PCU PSR: BSD15 (Bit 15)                               */
#define PCU_PSR_BSD15_Msk                 (0x8000UL)                /*!< PCU PSR: BSD15 (Bitfield-Mask: 0x01)                  */
#define PCU_PSR_BSD14_Pos                 (14UL)                    /*!< PCU PSR: BSD14 (Bit 14)                               */
#define PCU_PSR_BSD14_Msk                 (0x4000UL)                /*!< PCU PSR: BSD14 (Bitfield-Mask: 0x01)                  */
#define PCU_PSR_BSD13_Pos                 (13UL)                    /*!< PCU PSR: BSD13 (Bit 13)                               */
#define PCU_PSR_BSD13_Msk                 (0x2000UL)                /*!< PCU PSR: BSD13 (Bitfield-Mask: 0x01)                  */
#define PCU_PSR_BSD12_Pos                 (12UL)                    /*!< PCU PSR: BSD12 (Bit 12)                               */
#define PCU_PSR_BSD12_Msk                 (0x1000UL)                /*!< PCU PSR: BSD12 (Bitfield-Mask: 0x01)                  */
#define PCU_PSR_BSD11_Pos                 (11UL)                    /*!< PCU PSR: BSD11 (Bit 11)                               */
#define PCU_PSR_BSD11_Msk                 (0x800UL)                 /*!< PCU PSR: BSD11 (Bitfield-Mask: 0x01)                  */
#define PCU_PSR_BSD10_Pos                 (10UL)                    /*!< PCU PSR: BSD10 (Bit 10)                               */
#define PCU_PSR_BSD10_Msk                 (0x400UL)                 /*!< PCU PSR: BSD10 (Bitfield-Mask: 0x01)                  */
#define PCU_PSR_BSD9_Pos                  (9UL)                     /*!< PCU PSR: BSD9 (Bit 9)                                 */
#define PCU_PSR_BSD9_Msk                  (0x200UL)                 /*!< PCU PSR: BSD9 (Bitfield-Mask: 0x01)                   */
#define PCU_PSR_BSD8_Pos                  (8UL)                     /*!< PCU PSR: BSD8 (Bit 8)                